In many modern applications such as video processing, minimizing FPGA reconfiguration time is critical in order to avoid losing too many images. Partial reconfiguration is a technique that allows users to reconfigure a small part of the FPGA without impacting logical elements around it. Because a partial bitstream is smaller than a full one, it takes less time to reconfigure.
Sagem DS has devised a technique that allows FPGA designers to accomplish partial reconfiguration very fast. The all-hardware solution is based on a little state machine and the internal configuration access port (ICAP) interface for bitstream loading.