Delivering a Generation Ahead at 20nm & 16nm

The Xilinx All Programmable product portfolio based on 28nm and 20nm planar and 16nm Fin FET technologies keeps customers a generation ahead of their competition with an expansion of its offerings from three perspectives:

  • Portfolio: UltraScale™ architecture-based All Programmable FPGAs and 2nd generation 3D ICs and SoCs
  • Product: ‘Co-optimized’ with the Vivado™ Design Suite for extra performance, power, and integration
  • Productivity: Unmatched time to integration and implementation

Portfolio Direction

At 28nm, Xilinx expanded from FPGAs to three categories of All Programmable devices. This enabled a breakthrough in ‘programmable systems integration’ and corresponding advances for improved system level price/performance/watt -- moving both Xilinx and its customers a generation ahead of competition and in system value.

Xilinx is committed to staying a generation ahead with aggressive roadmaps across each of the three elements of its broader portfolio, with each element supporting and reinforcing the previous generation.


Figure 1: Xilinx continues to expand its leadership in all three areas.

Innovations at 20nm and 16nm

Xilinx has developed even more advanced FPGAs and 2nd generation SoCs and 3D ICs to stay a generation ahead, and deliver an extra node worth of performance, power, and integration. The UltraScale architecture was developed to scale from 20nm planar through 16nm and beyond FinFET (FF) technologies, and from monolithic through 3D ICs.  UltraScale, the industry’s only All Programmable architecture to deliver ASIC class performance, not only addresses the limitations to scalability of total system throughput and latency, but directly attacks the #1 bottleneck to chip performance at advance nodes: the interconnect.

All Programmable UltraScale Families

Laying the foundation for the rest of the portfolio, the core FPGA leverages the benefits of TSMCs 20nm SoC and 16nm FF process while incorporating a new set of design innovations for Xilinx’s UltraScale devices. These next generation devices deliver continued breakthroughs in price-performance-per-watt improvement, memory bandwidth and the next generation of industry leading system optimized transceivers.

Zynq UltraScale MPSoC – The 2nd Generation All Programmable SoC

The UltraScale™ MPSoC Architecture, built on TSMC’s 16nm FinFET process technology, enables next generation Zynq® UltraScale MPSoCs. This new architecture provides processor scalability from 32 to 64 bits with support for virtualization, the combination of soft and hard engines for real time control, and graphics/video processing, waveform and packet processing, next generation interconnect and memory, advanced power management, and technology enhancements that deliver multi-level security, safety and reliability. These new architectural elements are coupled with the Vivado® Design Suite and abstract design environments to greatly simplify programming and increase productivity.


Figure2 : The Xilinx UltraScale MPSoC architecture delivers the right engines for the right tasks.

2nd Generation All Programmable 3D IC

Xilinx UltraScale 3D ICs provide unprecedented levels of system integration, performance and capability. UltraScale 3D ICs contain a step-function increase in both the amount of connectivity resources and the associated inter-die bandwidth in this second-generation 3D IC architecture. The big increase in routing and bandwidth and new 3D IC wide memory optimized interface ensures that next-generation applications can achieve their target performance at extreme levels of utilization.

2nd Generation All Programmable 3D IC

Figure 3: Xilinx’s 2nd generation 3D ICs will come in homogeneous and heterogeneous configurations.

Next Generation Design Suite & Methodology

Built from the ground up for Xilinx’s 28nm portfolio, the Vivado Design Suite has been co-optimized with the UltraScale architecture to deliver significant quality of results, routability, utilization, and productivity advantages.  When combined with UltraFast™, a potent methodology that covers all aspects of board planning, design creation, design implementation and closure, programming and hardware debug, design teams will be able to accelerate their time to predictable success.

Productivity for the front end design process is multiplied by more than 4X with high level synthesis and IP integration tools. Productivity in design implementation improves by more than 4X due to faster hierarchical planning and analytic place and route engines as well as support for fast incremental ECOs.

Next Generation Design Suite

Figure 4: The Vivado Design Suite in conjunction with the UltraFast methodology enables unmatched time to integration and implementation.