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ASIC Prototyping & Emulation

Breakthrough performance and integration for ASIC prototyping and emulation can be realized with Xilinx UltraScale™ architecture. Virtex® UltraScale devices simplify design partitioning through high logic capacity, over 90% device utilization, ASIC-like clocking, enhanced routing, and high-speed transceivers for pin multiplexing. This breakthrough architecture coupled with Xilinx’s Vivado® Design Suite provides the ideal solution for tackling the demands of leading-edge ASIC and SoC platforms.

Solution Summary and Benefits

  • Breakthrough device capacity reduces the number of partitions and simplifies board layout
  • Enhanced routing and co-optimization with the Vivado Design Suite ensures over 90% device utilization
  • ASIC-like clocking efficiently maps complex ASIC and SoC clock trees
  • High-speed transceivers enable efficient pin multiplexing between FPGAs and support the I/O interfacing requirements for next generation systems
01_Virtex_CS1423_ASIC-Prototyping_Solutions_063014

UltraScale Architecture Benefits

  • Massive I/O Bandwidth
    • > 1 Tbps chip to chip bandwidth available
    • Low latency transceiver enables chip/chip interconnect
  • Massive Data Flow & Routing
    • Supports native wide ASIC busses with high performance
  • ASIC-like Clocking
    • Maximum flexibility for complex SoC prototyping
  • System Peformance
    • 15-30% performance improvement per device
    • 3X improvement due to reduced partitioning
  • Power Management
    • Up to 35% System Power reduction
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