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Data Center IP

Xilinx SmartCORE IP and LogiCORE™ IP for the Data Center provides system designers a head start on their project with proven, documented IP cores capable of executing a wide range of complex network functions—including traffic management, packet processing, TCP offload, cryptography, compression, and security—and all essential I/O interfaces including 1G/10G/40G/100G Ethernet MACs, PCIe Gen2 and Gen3, XAUI/XLAUI/CAUI, Serial Rapid I/O, SATA, and SAS.

Many of these proven IP cores are configurable so they can be tailored to specific application performance requirements. Xilinx offers specialists and design services to help customers adapt and use this IP to create Generation Ahead equipment designs.

Here is a comprehensive table of all the SmartCORE IP and LogiCore IP specifically used in data-center equipment design.

Flash Memory

Resource Type Provider

Advanced Flash Controller Interface (AFCI)

  • Multi-Port Architecture allows connecting up to 32 NAND devices (128 total NAND targets)
  • Separate administrative and I/O queues for flexible datapath management
  • Maximum of one register write per command submission/ completion
  • Industry standard bus interface (AXI-4) master used for command fetching, command completion, and data movement
  • Support for up to 64k commands per command queue
  • Independent R/W channels allow data movement from system to NAND and NAND to system concurrently
  • Actively maintains a command per NAND LUN for maximum throughput to/from the NAND
  • Automatic training sequence performed on a per-chip-enable basis
  • Firmware selectable taps for quick speed change via Set Features command
  • Selectable BCH-ECC correction capabilities based on NAND selection
  • Supports ONFI 3.2 and 4.0 compliant MLC and SLC NAND
  • Supports NV-DDR, NV-DDR2, Toggle 2.0
  • Optional: AES-XTS 256 bit encryption (P/N: IPC-BL157A-1-ZM)
  • The optionally available AES-XTS encryption algorithm is FIPS-197 certified
Alliance Member IP IntelliProp Inc. 

Flash Error Correction

Resource Type Provider

Flash Memory LDPC Flash Error Correction

  • Best-in-class code performance near Shannon limit
  • Achieved low error floor under 1e-15 with proprietary optimization method
  • Support for code rate change on-the-fly
  • Support both hard decision and soft decision decoding
  • High throughput and low latency performance
  • FPGA optimized for minimal area and power
LogiCORE IP Xilinx, Inc.

ECC with BCH Algorithm

  • High bandwidth, low latency parallel encode and decode paths
  • Configurable number of encode blocks
  • Configurable number of decode blocks
  • Configurable code word length (K), up to 8192 bytes
  • Configurable block size
  • Configurable 32, 64, 128, or 256 “FIFO” data interface 
  • Parallelized encoder
  • Parallelized decoder for syndrome calculations
  • User selectable error correction values (T)
  • User selectable field divisor allows for parallelized error search 
Alliance Member IP IntelliProp Inc. 

Network Traffic Management

Resource Type Provider

Traffic Manager

  • 32k queues
  • Five stages
  • SP+DWRR at each stage
SmartCORE IP Xilinx, Inc.

NIC Function

Resource Type Provider

Low Latency Ethernet MACs

  • Full 100G and 40G Ethernet line rate operation.
  • Optional Frame Check Sequence (FCS) checking, adding and deleting.
  • Static and dynamic de-skew functions.
  • PCS Lane Marker insertion and deletion.
  • PCS Lane framing and de-framing including swapping of each PCS Lane.
  • Inter-Packet Gap (IPG) insertion and deletion as required by 802.3ba
LogiCORE IP Xilinx, Inc.
Low Latency 25G Ethernet IP
  • Designed to the 25 Gigabit Ethernet Consortium specification
  • Base-R PCS sublayer operating at 25 Gb/s
    • Optional Auto-Negotiation
    • Optional FEC sublayer
  • Low latency
  • Configured and monitored through an optional AXI4-Lite Management interface or using status and configuration vectors
  • Comprehensive statistic gathering
  • Supports 802.3 and 802.1Qbb flow control
  • Supports VLAN and jumbo frames
LogiCORE IP Xilinx, Inc.

TCP Offload Engine

  • Ultra-Low Latency through 10 G TOE = less than 100 ns
  • Sustained large TCP payloads, depending upon remote server/client’s capability
  • 128 Session with scalable Payload FIFO of 8/16/32 K bytes
LogiCORE IP Intiliop

XAUI

  • Designed to 10-Gigabit Ethernet IEEE 802.3-2008 specification
  • Supports 20G double-rate XAUI (Double XAUI)using four transceivers at 6.25 Gb/s under features.
  • Supports 10-Gigabit Fibre Channel (10-GFC) XAUI data rates and traffic
  • Uses four transceivers at 3.125 Gb/s line rate to achieve 10-Gb/s data rate
  • Implements Data Terminal Equipment (DTE)
  • XGMII Extender Sublayer (XGXS), PHY XGXS, and 10GBASE-X Physical Coding Sublayer (PCS)
LogiCORE IP Xilinx, Inc.

Data Security / Compression

Resource Type Provider

AES Cryptography

  • Implements AES (Rijndael) to latest NIST FIPS PUB 197
  • Full dynamic support for all AES key sizes (128, 192 and 256-bits)
  • Supports data rates well in excess of 40Gbps
  • Separate cores provided for encryption and decryption
  • Roundkey generation can be split out for ultra low gatecount implementations
  • All AES operating modes easily implemented (eg. ECB, CBC, OFB, CFB, CTR, CCM, GCM, XTS, OCB)
Alliance Member IP Helion Technolgy Ltd.

LZRW3 data compression

  • Implements the LZRW3 lossless data compression algorithm
  • Supports data block sizes from 2K to 32K bytes with data growth protection
  • Completely self-contained; does not require off-chip memory
  • High performance; capable of data throughputs in excess of 1 Gbps
  • Ideal for improving system performance in data comms and storage applications
Alliance Member IP Helion Technolgy Ltd.

IPSEC and MACSEC Security Protocols

  • Performs hardware acceleration of IPsec ESP protocol to RFC 4303
  • Fully configurable to support all mandatory and proposed ESP-v3 confidentiality and integrity algorithms
  • Suitable for use in IPv4 and IPv6 IPsec Transport and Tunnel mode applications
  • Implements Extended (64-bit)
  • Sequence Number for IKEv2 support
  • Supports all ESP security service
  • combinations
  • Supports Gigabit/sec throughputs
  • Supports insertion of padding for
  • Traffic Flow Confidentiality (TFC)
  • Performs automatic ESP padding
  • generation and checking
Alliance Member IP Helion Technolgy Ltd.

AES/XTS Encryption Core

  • Full Verilog Core
  • 128 or 256 bit selectable AES encryption
  • The AES-XTS algorithm is FIPS-197 certified
  • The encode and decode channels are made to look and act like independent FIFOs for ease of integration. The control block has a register interface to be easily managed by a hardware state machine or controlled by a processor for operations such as key initialization, and TWEAK configuration and management.
  • Programmable number of pipeline paths allows the user to balance area/bandwidth requirements. The number of parallel pipelines can be configured to support high performance/high throughput applications as well as lower performance and/or resource limited applications.
  • The core has a simulation test bench and register initialization sequence to support rapid integration
  • Processor and RTL control interface
  • Independent Cipher/Inverse Cipher key management
  • Concurrent read and write support
  • Bypass functionality to send data through the Core unmodified
  • Supports integer multiples of 16 byte Data Unit sizes
  • Verilog/VHDL support
Alliance Member IP IntelliProp Inc.

System Interconnect

Resource Type Provider

QuickPath Interconnect (QPI)

  • Designed for High-speed FPGA-to-processor communications
  • Cache agent, with full-width (20 lanes) operation at 6.4Gbps per lane
  • Example design, for rapid start-up, based on Xilinx® Virtex®-7 FPGA
SmartCORE IP Xilinx Inc.

PCIe Gen2 and Gen3

Resource Type Provider
  • PCI Express™ Base Specification Revision 3.0/2.0/1.1 compliant
  • x1, x2, x4, x8, x16 lane support
  • 8.0, 5.0 & 2.5 Gbit/s SERDES suppor
  • Endpoint and Root Port support
  • 32, 64, 128 and 256 bit Core widths to enable user to match core speed with process capability
  • AER, ECRC, MSI-X, Multi-Vector MSI, Lane Reversal support
Alliance Member IP

Northwest Logic

PLDA

Storage Interface

Resource Type Provider

Serial ATA (SATA)

  • Fully compliant to the SATA 1.5Gb/s, 3.0Gb/s, and 6.0Gb/s industry specifications
  • Transport or AHCI or Application or Application Register (ARI) interface options
  • Data Interface through FIFOs
  • Supports either Seres, PIPE, or SAPIS interface
Alliance Member IP Intelliprop Inc.

Serial Attached SCSI (SAS)

  • Fully compliant to the SAS 6.0Gb/s industry specifications
  • AHB-Lite and FPGA specific interfaces for register access
  • Supports either SERDES or PHY layer interface
  • Fully verified with SAS Verification IP
Alliance Member IP Intelliprop Inc.

NVMe Host/Initiator Core

  • Fully compliant to the NVM Express 1.2.1 industry specification
  • Compliant with 3rd party PCIe Root Complex IP cores
  • Automated initialization process with PCIe Hard Block
  • Automated command submission and completion
  • Scalable I/O queue depth
  • Support for 64k outstanding I/O commands
  • Scalable data buffer size up to 1GB
  • Processor or State Machine driven interface
  • Submission queue command context error prevention
  • Support for block sizes from 512 byte to 16kB
  • Application layer (command based) interface with Processor interface
  • Verilog support (VHDL wrappers only)
Alliance Member IP IntelliProp Inc.

NVMe Device/Target Core

  • Fully compliant to the NVM Express 1.2.1 industry specification
  • Compliant with 3rd party PCIe Target IP cores
  • Application layer (command based) interface with Processor interface
  • Data Interface through FIFOs
  • Processor interface for register access
  • Command interrupts for user processing system
  • Synthesis time maximum queue depths of up to 64k supported
  • Automated PCIe interrupt generation on posting of completions
  • Synchronous design for easy integration
  • Verilog and VHDL wrappers 
Alliance Member IP IntelliProp Inc.
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