The Intel® QPI protocol provides a low-latency, high-bandwidth serial link for processor-to-processor communications. In the block diagram below, an existing design employs a second X-86 microprocessor to add four PCIe ports to a server processor while a separate NIC ASSP adds Ethernet ports to connect to the data center’s LANs and SANs. One FPGA can perform both sets of functions while delivering twice the performance, with lower BOM cost and at half the power consumption.
By leveraging the QPI IP core and the power of Xilinx 7 series All Programmable devices, developers of next-generation data center servers and appliances can effectively:
Solution Summary and Benefits
To learn more about Xilinx Data Centers Solutions, visit the Data Center IP and Reference Design page.