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Semiconductor Automated Test Equipment

Xilinx’s comprehensive solutions enable next
generation SoC and Memory test platforms

Next generation SoC testers need to test a broader range of IO protocols, which have increasing complexity and speed. Xilinx’s SerDes and HSSIO technology offers the most flexibility at the right cost point to realize high volume SoC and Memory testers. Integrated Hard IP for memory controllers and Chip-to-Chip interconnect realize resource and cost effective solutions.

Design Examples Description Device Support

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Semi-ATE: Image Acquisition
Image Acquisition requires high performance transceivers and DSP capability while keeping the power consumption and device cost low for this cost sensitive application. Kintex® UltraScale+™ provides the best price/performance/watt balance delivering the most cost-effective solution for high-end capabilities including 32Gbps transceivers, 6.3 TeraMACs of DSP compute performance, 2.6Gbs DDR4 and PCIe Gen4x8 support.

Kintex UltraScale+


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Semi-ATE: PIN Electronics
PIN Electronics calls for cost effective FPGA for vector generation and analysis as well as large number of high performance IOs to connect to large number of ASSPs with parallel interfaces. Given the 1Gbps+ link speed, unfriendly channel and fewer reference clocks, the IO buffers and clock generation/distribution capability needs to be sophisticated to manage skew across multiple lanes and over PVT. Kintex UltraScale+ has high performance and feature rich SelectIO transceivers with signal conditioning capabilities, PLL and DLL based clock generation and distribution resources, and skew management capabilities. This makes Kintex UltraScale+ ideally suited for PIN Electronics application.

Kintex UltraScale+

Developer Zone

For FPGA designers looking to shorten design time and ensure scalability and re-use, Xilinx provides a comprehensive suite of solutions ranging from C-based design abstractions to IP plug-and-play to address bottlenecks in hardware development, system-level integration, and implementation.

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