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Wired & Wireless Testers

Enabling Next Generation Testers for Data Center, Wired and Wireless Networks

Data Center testers require high bandwidth, high IO count solutions as well as efficient implementation of PMA, PCS and MAC functions. Xilinx UltraScale and UltraScale+ families offer the highest IO bandwidth and most efficient implementation using the hard IP blocks for MAC and FEC.

Wireless testers need integrated solutions with a rich mix of DSP, IO and memory. UltraScale+ offers a compelling mix at lower power, enabled by 16nm FinFET process, which is critical for handheld tester applications.

Design Examples Description Device Support

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Mobile Phone Tester
Mobile Phone Tester emulates a network and as such requires FPGAs with rich set of DSP and memory to implement the PHY layer functions of different cellular protocols. Support for different parallel and serial IO interfaces is also needed to interface to DAC/ADC, DSP and Memory banks. Kintex® UltraScale+™ offers the best price/performance/watts to realize high performance Mobile Phone Tester.

Kintex UltraScale+


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Ethernet Tester: Layer 1-3
Xilinx’s Virtex UltraScale+™ with its high performance SerDes enables high bandwidth interconnect to optics, backplane and Chip-to-Chip. For connecting directly to Optics, GTY transceivers supports 25Gps thru-put over OIF VSR channel. It also has integrated Ethernet MAC w/RS-FEC and OTN modes saving over 150K LUTs per 100G Channel. For Chip-to-Chip interface, it has Hard IP for PCIe 4.0 and Interlaken saving additional logic and power. For control, quad core Zynq® UltraScale+™MPSoC devices together with the SDSoC™ development flow provide ideal platform to build data-flow control, tracking and reporting software.

Virtex UltraScale+

Zynq UltraScale+ MPSoC

Developer Zone

For FPGA designers looking to shorten design time and ensure scalability and re-use, Xilinx provides a comprehensive suite of solutions ranging from C-based design abstractions to IP plug-and-play to address bottlenecks in hardware development, system-level integration, and implementation.

Xcell Daily Blog

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