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Ultimate Flexibility and Features without Sacrificing Price, Performance, or Power

The demands for dynamically managed packet-based processing continues to climb at unprecedented levels fueled by the explosion of open collaboration services, advancements in mobility and social networking, proliferation of smart devices, as well as unification of quality of experience (QoE) demands across service provider and enterprise segments.

Xilinx delivers a variety of Smarter Solutions expanding traffic control, prioritization and monitoring capabilities to the granularity of single packet, individual session or application. These solutions enable network equipment to inspect and manipulate packet headers and payload contents, and to dynamically apply sophisticated routing policies. These Xilinx Smarter Solutions also integrate easily with security, cryptography and RegEx functions.

Xilinx Smarter Solutions for Packet-Based Processing include the FPGAs, 3D ICs, and SoCs in addition to a suite of SmartCORE IP that can be customized to optimally address unique market needs. The Xilinx Vivado™ Design Suite and the Communications Design Center provide a faster, more flexible means to go to market with greater differentiation, lower risk and lower total cost of ownership than alternative ASIC and ASSP solutions.

Sample applications served by the Xilinx Packet-Based portfolio includes Core Routing /Switching, Software Defined Networking, Next Generation Routing and “Quad-Play Plus” services. Please talk to a Xilinx sales representative about your specific needs.


Xilinx Smarter Solutions for Packet-Based Processing include:

  • Hierarchical Per-Flow Traffic Manager with highly parameterizable features tunable to domain-specific configurations
  • Flexible interface options:1Gbps/10Gbps/40Gbps/100Gbps/Interlaken allow customer proprietary I/F
  • Flexible CPU interface options: Ethernet and PCIe® allow customer proprietary I/F
  • Supports minimum Ethernet packet size (at full line-rate) and jumbo frames
  • Permits significant value differentiation via integration of customer-specific configuration “know-how” and proprietary blocks via custom integration by Xilinx Communication Design Center
  • Unified architecture scalable across bandwidth--10Gbps to 100Gbps (200Gbps upcoming) and 2K to 64K of queues all features dynamically programmable via standard APIs
  • User-transparent data base management with advanced memory packing
  • Optimal memory utilization to address specific instantiation and data base structures
    • Low bandwidth/low queue count configurations fully supported within internal Block RAM
    • High bandwidth/high number of queues utilize a combination of Block RAM and [FPGA] industry highest I/O bandwidth supporting dense memory configurations supporting:
      • DDR3 @ 1866Mbps, RLDRRAM3 @ 800MHz, and QDRII+ @ 500MHz
  • Scalable architecture enabling up to 5 levels of scheduling hierarchy, where each level could be independently configured with policing, shaping, scheduling and congestion/flow control features
  • Full support for broadcast and multicast
  • Congestion control: TD, RED, and WRED
  • Flow control -per queue/per aggregate of queues per hierarchy
  • Scheduling: SP, Deficit Weighted Round Robin(DWRR), patent pending SP+ (for optimal combination of scheduling functions)
  • Policing: discard or marking based on srTCM, trTCM, and mefTCM
  • Statistics: per queue, per aggregate, per hierarchy covering all events
  • Extensive IP monitoring facility with interrupts and status accessible via APIs
  • Reference design on Virtex®-7 FPGAs offering 32K queues and 3 levels of hierarchy available for demos by Xilinx FAE and architects
  • Major advances in network programming enabling rapid networking stack development
  • Intuitive declarative packet-oriented programming language speeds packet parsing including header and payload
  • Suite of advanced compilation tools enabling generation of RTL that is tuned to Xilinx FPGA architecture
  • Netlist generation guided by various parameters
    • Protocols
    • Packet formats
    • Compilation-time optimization parameters
      • FPGA family/device
      • Bus width
      • Clock frequency, etc.
  • Parser output processed by Xilinx FPGA tool chain (ISE® or Vivado Design Suites)
  • Parser can examine data streams of any length with fixed or variable space between sequential fields
  • Tool chain allows static implementation with fixed configurations for FPGA families/devices
  • Advanced options enable in-socket programmability (initial product rollout will require Xilinx customization service via CDC)
  • Extensive IP monitoring facility with interrupts and status accessible via APIs
  • Reference design on Virtex-7 device offering 5-tuple parsing examples available for demos by Xilinx FAE and architects

Design Example

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