Software Defined Specification Environment for Networking

Enabling ‘Softly’ Defined Networks

The Software Defined Specification Environment for Networking (SDNet) in conjunction with Xilinx All Programmable FPGAs and SoCs allows for the creation of ‘Softly’ Defined Networks, a technology dislocation that goes well beyond today’s Software Defined Networking (SDN) architectures.

Introducing ‘Softly’ Defined Networks

‘Softly’ Defined Networks supports SDN functionality while also allowing for game changing differentiation through software programmable data plane hardware with content intelligence that dynamically collaborates with control plane SW while addressing the performance, flexibility, and security challenges of modern content-oriented networking.


The SDNet specification environment enables multiple disruptive capabilities including:

  • Support of wire speed services that are independent of protocol complexity
  • Provisioning of per-flow, flexible services
  • Support for revolutionary in-service “hitless” feature updates while operating at 100% line rate

These unique capabilities enable carriers and MSOs to dynamically provision unique, differentiated services without any interruption to the existing service or the need for hardware re-qualification or truck roll. This provides service providers higher revenue potential with unprecedented CapEx, OpEx, and time to market savings.  Network equipment providers realize similar benefits from the feature rich, flexible Softly Defined Network platform which allows for extensive differentiation through the deployment of content-aware data plane hardware that is specified by the SDNet environment.

Additional benefits of Softly Defined Network solutions enabled by SDNet and Xilinx’s All Programmable FPGAs and SoCs include:

  • Improved, highly flexible Quality of Service (QoS)
  • Flow and session aware capabilities
  • Fully programmable hardware data plane and I/O
  • Support for NFV at wire speed including user defined, custom capabilities
  • Scalable line rates from 1G to 400G

The graphic below demonstrates how system architects can unleash the benefits of All Programmable technologies to realize smarter, softly defined networks without requiring a detailed knowledge of the underlying All Programmable device architecture. This implementation flow also allows system architects to focus only on the services they are looking to provision, without having to focus on exactly how those services are being implemented.


SDNet enables the ability to use high-level specifications in conjunction with application optimized libraries and the associated design environment to automatically transform the specifications into an optimized hardware implementation on Xilinx All Programmable devices that delivers line rate performance at optimal cost, power and performance.

Additional Xilinx Smarter Solutions for Packet-Based Processing include:

  • Flexible interface options:1Gbps/10Gbps/40Gbps/100Gbps/Interlaken allow customer proprietary I/F
  • Flexible CPU interface options: Ethernet and PCIe® allow customer proprietary I/F
  • Supports minimum Ethernet packet size (at full line-rate) and jumbo frames
  • Permits significant value differentiation via integration of customer-specific configuration “know-how” and proprietary blocks via custom integration by Xilinx Communication Design Center
  • Unified architecture scalable across bandwidth--1Gbps to 100Gbps (200Gbps upcoming) and 512 to 64K of queues all features dynamically programmable via standard APIs
  • User-transparent data base management with advanced memory packing
  • Optimal memory utilization to address specific instantiation and data base structures
    • Low throughput configurations and low queue count configurations fully supported within internal Block RAM
    • High throughput and high queue count configurations utilize optimal combination of Block RAM and [FPGA] industry highest I/O bandwidth supporting dense memory configurations including :
      • DDR3 @ 1866Mb/s, DDR4 @ 2400 Mb/s RLDRRAM3 @ 800MHz, and QDRII+ @ 500MHz
  • Scalable architecture enabling up to 5 levels of scheduling hierarchy, where each level could be independently configured with policing, shaping, scheduling and congestion/flow control features
  • Full support for broadcast and multicast
  • Congestion control: TD, RED, and WRED
  • Flow control -per queue/per aggregate of queues/ per hierarchy level
  • Scheduling: SP, Deficit Weighted Round Robin(DWRR), patent pending SP+ (for optimal combination of scheduling functions)
  • Policing: discard or marking based on srTCM, trTCM, and mefTCM
  • Statistics: per queue, per aggregate, per hierarchy covering all events
  • Extensive IP monitoring facility with interrupts and status accessible via APIs
  • Traffic Manager demonstrations on Virtex®-7 FPGAs offering 32K available for demos by Xilinx FAE and solution architects
  • Major advances in network programming enabling rapid networking stack development
  • Intuitive high-level networking specifications post-processed by Xilinx development tools speed packet header and payload parsing
  • Suite of advanced compilation tools enabling generation of RTL that is tuned to Xilinx FPGA architecture
  • Netlist generation guided by various parameters
    • Protocols
    • Packet formats
    • Compilation-time optimization parameters
      • FPGA family/device
      • Bus width
      • Clock frequency, etc.
  • Parser SmartCore rtl natively recognized and processed by Xilinx Vivado Design Suites
  • Parser can examine data streams of any length with fixed or variable space between sequential fields
  • Tool chain allows static implementation with fixed configurations for FPGA families/devices
  • Advanced options enable in-socket programmability (initial product rollout will require Xilinx customization service via CDC)
  • Extensive IP monitoring facility with interrupts and status accessible via APIs
  • Parsing examples for Virtex-7 devices available for demos by Xilinx FAE and solution architects

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