Baseband
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Accelerate LTE Basestation Design and Development
Baseband processing represents a key area for product differentiation. With the advent of LTE, increased datarates, reduced latencies and the use of more advanced algorithms mean that traditional programmable DSP based architectures no longer offer optimal solutions for channel card designs. Xilinx FPGAs provide massive levels of parallel processing power to simplify designs, reducing system cost, power dissipation and form factor. In addition, the inherent reconfigurability and scalability of Xilinx FPGAs reduces the risk of expensive redesigns as standards evolve.
The Xilinx LTE Baseband Targeted Design Platform brings together an extensive range of both generic and LTE-specific air interface IP, a comprehensive design environment and pre-validated Targeted Reference Designs. By providing pre-built, highly optimized 3GPP-LTE layer-1 components, the LTE baseband platform enables developers to focus on product differentiation rather than the implementation of complex physical layer functions.
- Design with high reliability with pre-optimized and validated IP
- Support all channel card architectures and system configurations
- Increase efficiency with advanced MIMO technology
- Overcome increasing ASIC development costs
Cost and Power-optimized Baseband
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With easy-to-use graphical user interfaces, developers can configure LTE Baseband Targeted Design Platform LogiCORE™ IP components to optimize for cost and power regardless of the target basestation configuration. For example, the LTE Turbo Decoder can be generated with either 1, 2, 4 or 8 parallel decode units resulting in resource-optimized implementations across the full range of form factors from femtocell to the most complex macrocell systems. Developers can integrate production-quality LTE baseband functions from Xilinx into existing designs or customize the Xilinx LTE Targeted Reference Designs to leverage their own value-added technology.
Alleviating Data Flow Latency in Typical Co-processor Baseband Design
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The low-latency performance requirements of 3GPP-LTE put a strain on data flow between the DSP and FPGA, creating a bottleneck in typical baseband design. The Xilinx LTE Channel Uplink and Downlink LogiCORE™ IP alleviates the bottleneck created by integrating more of the baseband processing within the FPGA, brining additional benefits in reduced cost and power.
Comprehensive LTE eNodeB Reference Design
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The LTE Baseband Targeted Design Platform in conjunction with the Multi-mode Radio Targeted Design Platform creates an end-to-end LTE basestation design encompassing radio, baseband, media access control (MAC), and transport functions.