Connectivity Interfaces for Wireless

The movement from traditional centralized basestation architectures to distributed architectures relying upon remote radio heads is giving way to standards-based protocols — in place of expensive proprietary connectivity interfaces—between the baseband and radio card. Xilinx offers fully tested and verified Wireless IP and Reference Designs

IP cores and reference designs to support multiple standards-based connectivity interfaces for wireless infrastructure equipment including:

• CPRI™ and OBSAI for interfacing between the channel card and remote radio head
• Serial RapidIO (SRIO) for channel card multi-processor interconnect
• JESD204A in radio heads for interfacing to data converters
• PCI Express® and Gigabit Ethernet for simplified system integration with the backplanes and general control processors

Designed for FPGA architecture, these programmable blocks help developers drive down costs and meet lower power requirements while also allowing customization, product differentiation, and easy updates to match evolving specifications and design requirements.