Frequently Asked Questions about the CoolRunner-II CPLDs

What is the CoolRunner-II family?
The CoolRunner-II family is the next generation Xilinx CPLD, based upon the best features of the Xilinx XC9500 and CoolRunner XPLA3 families. The CoolRunner-II solution was designed specifically to address the challenge facing CPLD designers dealing with the trade-off between high performance and low power consumption. CoolRunner-II is a 1.8V device that provides performances up to 300MHz and estimated power consumption of less than 100 micro amps CoolRunner-II CPLDs combine the high speed and ease of use of the XC9500 CPLD family with the ultra low power consumption of the CoolRunner XPLA3 family. Enabled by second generation Fast Zero Power™ (FZP) design technology, CoolRunner-II CPLDs offer advanced system features and low power operation. The CoolRunner-II devices allow the integration of discrete system functions into a single reprogrammable device, resulting in lower costs, higher reliability, faster time to market, and smaller designs.

What is Fast Zero Power (FZP)?
Fast Zero Power (FZP) is the patented design technology utilized in CoolRunner XPLA3 and CoolRunner-II devices that enables high-speed, low power programmable logic devices. As a replacement technology for the sense amplifier found in competing CPLDs, Fast Zero Power represents a programmable logic breakthrough that minimizes system current demand and allows small chip-scale package options. Low power designs are enabled through FZP by using true CMOS both in process technology and design technique.

What is a sense amplifier?
A sense amplifier is the traditional way to create a CPLD product term. Sense amplifiers employ a bipolar design technique that helps the product-term array achieve fast propagation delays. However, sense amplifiers consumer a large amount of power -- even in standby mode.

What are the advantages of Fast Zero Power?
Fast Zero Power uses virtually no standby current, puts no power limits on device size, and combines high performance and low power.

What are the applications for CoolRunner-II CPLDs?
The CoolRunner-II family offers a solution for both "plugged" and "unplugged" digital consumer electronics products such as PDAs, cell phones and satellite set-top boxes. CoolRunner-II CPLDs also address the requirements of markets as diverse as telecommunications, data communications, and industrial control.

What advantages do CoolRunner-II CPLDs have over competing products?
At the current time, no Xilinx competitor provides a 1.8V, low power, high speed CPLD with low standby current. Moreover, CoolRunner-II CPLDs offer unique Xilinx features such as a clock divider and clock doubler (CoolCLOCK), a programmable on/off switch for power management (DataGate), advanced I/O support (SSTL, HSTL) and flexible output banking.

What are the devices in the CoolRunner-II family and what packages are available?
Unlike competing products, Xilinx CoolRunner-II CPLDs provide a wider range of package offerings and more I/Os in high-density devices. The following table summarizes key specifications for the CoolRunner-II CPLDs.

Devices	XC2C32	XC2C64	XC2C128	XC2C256	XC2C384	XC2C512
Macrocells	32	64	128	256	384	512
tpd (ns)	3.5	4	4.5	5	6	6
Max User I/O	33	64	100	184	240	270
Packages
	VQ44	VQ44
	PQ44	PQ44
	CP56	CP56
		VQ100	VQ100	VQ100
			CP132	CP132
			TQ144	TQ144	TQ144
				PQ208	PQ208	PQ208
				FT256	FT256	FT256
					FG324	FG324

What are the differences between the CoolRunner XPLA3 and CoolRunner-II families?
The CoolRunner-II family is manufactured on 0.18 micron process and runs with a core operating voltage of 1.8V and I/O voltages of 1.5V, 1.8V, 2.5V, and 3.3V. By comparison, the earlier CoolRunner XPLA3 family operates at3.3V with 5V tolerant I/Os. In addition, CoolRunner-II CPLDs provide output banking in 128 macrocell devices and larger, extend the low power offering of the XPLA3 by as much as 50 percent, offer higher speed grade performance to 300MHz, add support for clock dividers and clock doublers, and provides advanced design security.

What are the differences between 9500XV and CoolRunner-II families?
The CoolRunner-II family is manufactured on 0.18 micron process and runs with a core operating voltage of 1.8V and I/O voltages of 1.5V, 1.8V, 2.5V, and 3.3V. By comparison, the XC9500XV CPLDs have a 2.5V core with I/O voltages of 1.8V to 3.3V. CoolRunner-II CPLDs also offer wider I/O support for SSTL and HSTL, the enhanced CoolRunner low power architecture, new clocking features like clock dividers and clock doublers, and advanced design security.

What are the similarities between the CoolRunner-II family and the CoolRunner XPLA3 family?
CoolRunner-II and CoolRunner XPLA3 both provide a PLA product term allocation and Fast Zero Power architecture and feature low power.

What are the similarities between the CoolRunner-II family and the 9500XV family?
CoolRunner-II and 9500XV both feature bus hold, I/O banking and high performance.
Are CoolRunner-II CPLDs pin-to-pin compatible to prior Xilinx CPLD offerings? No. Due to the complex layout of CoolRunner-II devices, it was not possible to match pin/ball assignments in similar packages.

What are the architectural differences between the XC9500XV, XPLA3 and CR-II?
The following table summarizes the architectural differences of Xilinx CPLDs.

What are the CP56 and CP132 packages?
Xilinx leads the industry with the introduction of the small, space-efficient Chip Scale Package (CSP). This advanced technology uses 0.5mm-ball spacing and is ideal for applications that need the smallest board area possible. Xilinx CP56 and CP132 solutions offer one of the smallest form-factor packages available today for a CPLD, taking up less board space, and allowing for a smaller overall end product.

What's the differences between the CS and CP packages?
The CS packages uses 0.8mm ball spacing and the CP packages uses 0.5mm spacing.

What software supports the CoolRunner-II?
Both ISE WebPACK and Foundation ISE 4.1I offer CoolRunner-II support. ISE WebPACK is now available without charge from www.xilinx.com.

What are the advantages of WebPACK?
WebPACK is a free, downloadable desktop solution that handles device designs in all Xilinx products except the largest Virtex FPGAs. WebPACK requires no license and enables designers to immediately start designing.
What programming tools support CoolRunner-II?
Impact.

How will the additional performance and system features found in the CoolRunner-II family benefit the customer?
Customers will no longer have to sacrifice high performance for low power. What is the difference between a PAL and a PLA? The PAL (Programmable Array Logic) has a programmable AND array with a fixed OR array. The PLA (Programmable Logic Array) has both a programmable AND array and a programmable OR array. CoolRunner is a PLA.

What are the benefits of the PLA architecture?
The PLA architecture allows sharing of product terms instead of recreating duplicate product terms and excellent pinout retention with identical performance.

What speed and temperature grades are there for the CoolRunner-II family?
CoolRunner-II will have 3 commercial speed grades and 2 industrial speed grades.