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Home : Press Room : Press Kits : ISE Press Kit : 250 New ISE Features 250 New ISE Features

Top 25

Support for native Redhat Linux
Automatic local clock placer support in Virtex-II & Virtex-II Pro
Automatic hold time elimination in the router
Service pack auto-detection using WebUpdate
Project Navigator support for mixed language synthesis flow with Synplify Pro and XST
New Project Wizard in Project Navigator
Improved routing delay estimator for better performance
Advanced timing-driven packing and placement, including effort-level control
PACE can now be used for initial pin preassignment and write out VHDL and Verilog
PACE can now read and write CSV (MS-Excel) and interface to PCB tools
PAD Report generated in ASCII text and CSV (MS-Excel) for use with PACE
Errors/Warnings tab in ProjNav Console brings messages from all applications to single window
Offset constraint enhanced to support source synchronous interfaces
Added clock jitter attribute for Period constraints
Ability to add the processor portion of an Embedded Development Kit (EDK) design to a project
Enhanced Core Generator integration in Project Navigator
New integration with Synplify Schematic Viewers
Added integrated support in Project Navigator for 3rd party editors - Ultraedit and Codewrite
Simplification of PAR effort levels
Incremental Enabled mode preserves module boundaries even if not registered
Package flight time used in timing analysis
SSO rules checking in PACE
Clock region display in PACE
Local clock pin selection in PACE
Cadence NCsim simulation speed improvements

Project Navigator
1. WebUpdate can auto-detect new service packs and download only files needed
2. New Project Wizard
3. Support for mixed language synthesis flow with Synplify Pro and XST
4. IP for both Architecture Wizard and CORE Generator™ are now displayed in a single list
5. Ability to add the processor portion of an Embedded Development Kit (EDK) design to a project
6. 'New Source' and 'Add Source' processes added to Process Window
7. Automatically create/add UCF when a constraint process is run
8. New Errors/Warnings tab in Console
9. Application icons added to Process Window
10. Tip of the Day
11. Improve VHDL Library handling
12. VHDL entities and architectures can be in different files
13. Improve ease of creating user libraries and adding source files
14. Improve detection and reading of libraries in added source files
15. Compile user libraries as part of .ldo script
16. Allow sharing libraries between projects
17. Improve HDL Package handling
18. Added Process for HDL Simulation Library compilation
19. Support Verilog Test Fixtures with industry standard .v extension
20. Added support for Coregen/Arch Wizard modules in EDIF Design Flow
21. Added 'Other Command Line Options' to Advanced Property set
22. Enhanced Incremental Design support
23. Enhanced Core Generator integration
24. Availability of Synplify GUIs within the Synplify integrated flow
25. New integration with Synplify Schematic Viewers
26. Enhanced Leonardo Spectrum integration
27. Enhanced ModelSim Integration
28. Enhanced iMPACT integration
29. Enhanced 3rd party tool detection/selection
30. Enhanced Chipscope integration
31. Enhanced XST RTL Viewer Integration
32. Enhance UCF Integration
33. Enhanced XPower integration with ISE
34. Added user preference for specifying tool to open UCF in when UCF is double-clicked
35. Added integrated support for 3rd party editors - Ultraedit and Codewrite
36. Support new PACE features
37. Improved support for large designs, including System Generator for DSP designs
38. Optimized organization of output files in project directory
39. Viewing of application processes in Snapshots
40. Design Examples summary table
41. Mixed-language simulation support
42. Embedded browser for viewing CPLD fitter report and Xilinx on the Web
43. Simplified PAR effort levels
44. Support for creating Synopsys Primetime Timing Analyzer netlists
45. Integrated HDL Bencher into ProjNav framework
46. GUI creation of Conformal netlists
47. GUI creation of Synopsys Formality netlists
48. New XST options added to XST synthesis properties
49. New pushbutton flow look and feel for CPLDs
50. Properties are centralized in one place - no need to look under different processes
51. Enhanced autodetection of integrated partner synthesis and simulation tools
52. User selectable preference for ucf editor
53. Faster Core Generator startup
54. Enhanced design state indication
55. Streamlined CPLD processes
56. Support for VHDL entities and architectures in separate files
57. Automatic project migration
58. Entity-Instance Source view
59. MPPR integration improvements
60. UUT instance name option added to verilog simulation options
61. Automatic package recognition and ordering
62. User Controlled Compile Order
63. Dependant properties enhanced
64. Device Family list optimized

PAR

65. Automatic local clock placer support in Virtex-II & Virtex-II Pro when map -timing flow is used
66. Automatic Hold time elimination in the router
67. Improved Routing Delay Estimator for better performance
68. Improved Global Clock Placer to fully support Clock Regions in Virtex2/Pro Spartan3.
69. Simplification of PAR effort levels from 5 to 3
70. Delay report generated on demand only
71. Three formats of the PAD file generated automatically during PAR.
72. Some support for automatic floorplanning of RANGELESS AREA GROUPs.
73. Support for a Clock Region Constraint
74. Option to override timing driven mapper placement.
75. Report peak memory usage in the PAR report.

MAP

76. Advanced timing-driven packing and placement, including effort-level control
77. Detailed resource utilization reporting
78. Enhanced trimming rules for incomplete designs ("-u" option)

Timing

79. Offset constraint enhanced to support source synchronous interfaces
80. Individual pin flight times for flip chip packages taken into account
81. Added clock jitter attribute for Period constraints
82. Fastest path reporting for hold times
83. Hold errors reported in separate section
84. DCM feedback constraint allows specification of external delay
85. Clock skew calculated between related clocks without common source
86. Datasheet report includes clock phase relationships
87. User Defined Paths setup improved
88. Improved DRC's within Timing Improvement Wizard
89. Timing Analyzer indexes Setup/Hold paths by constraint name
90. Add more detail to datasheet report
91. Report maximum memory used running TRCE
92. Improve accuracy of DCM error calculation
93. Provide way to analyze a specific path without changing timing constraints
94. Allow NET TIGs to be selectable as when analyzing against timing constraints
95. Can now close all timing reports with one selection
96. Can now save all reports with one selection
97. Find operation can now be case insensitive in the analyzer
98. Allow copy from timing analyzer console window
99. Add high level functions like CPUs and Mulitpliers to be selectable in the "analyze against" mode
100. Timing Analyzer can be run with a Macro File without opening the GUI
101. Timing Analyzer now shows valid ranges for temperature and voltage prorating
102. The net delay report can now show estimates for unrouted nets
103. The net delay report can now report in picoseconds
104. The Timing Analyzer can now accept spaces in file names

PACE

105. PACE can now be used as initial pin entry tool
106. Package flight time display
107. SSO rules checking
108. Clock region display
109. Local clock pin selection
110. Ability to read and output Verilog
111. Ability to read and output VHDL
112. Ability to read and output CSV (MS-Excel)
113. Pin swap group for board layout considerations
114. Automatic bus grouping
115. Added support for multiple CPLD constraints (KEEP, OPEN_DRAIN, PWR_MODE, …)

Floorplanner

116. BEL support - locating FFs/LUTs to speciific sites within slices
117. RPM creation can directly create "self-contained core" (NGC format)

XST

118. Support of mixed language projects
119. Support for Assert statements in VHDL.
120. Improved complex data type (records, array of records, etc.) in VHDL.
121. Improved synthesis time for structural designsin VHDL.
122. Support for generate statements in verilog.
123. Support for indexed vector part selects in verilog.
124. Support for array bit and part selects in verilog.
125. Support for module array instantiations in verilog.
126. Macro inference of counters with modulo.
127. Macro inference of multipliers with constant (KCM).
128. Macro inference of block RAMs with reset.
129. Macro inference of RAM initialization via signal declaration mechanism.
130. Finite State Machine (FSM) Processing.
131. Improved FSM recognition.
132. Support for Mealy FSMs.
133. Detection of unreachable FSM states.
134. FSM implementation in Block RAM
135. Cores Search Directories switch (-sd).
136. New value for Keep Hierarchy constraint (KEEP_HIERARCHY) : soft.
137. New value for Netlist Case constraint (CASE): maintain for VHDL and mixed language projects.
138. FSM Style constraint (FSM_STYLE).
139. Signal Encoding Algorithm constraint (SIGNAL_ENCODING).
140. New value for Multiplier Style constraint (MULT_STYLE): kcm.
141. Support for mapping of logic on Block RAM (BRAM_MAP).
142. Use Carry Chain constraint (USE_CARRY_CHAIN).
143. New values for Box Type constraint (BOX_TYPE): primitive.
144. Optimize Instantiated Primitives switch (-optimize_primitives).
145. Buffer Type constraint (BUFFER_TYPE).
146. Library Search Order switch (-lso ).
147. Improved Timing constraints support.
148. Mapping of general logic on Block RAM via Map Logic on BRAM (BRAM_MAP) constraint.
149. Improved HDL Advisor (all such messages are referenced as "HDL Advisor" ).
150. Improved HDL reporting.
151. Verbosity control via Hide Messages (XIL_XST_HIDEMESSAGES) environment variable.

Partner

152. Create SDF with max and relative min values for Primetime
153. HSPICE Signal Integrity Simulation (SIS) software now supports S-parameter models for RocketPHY
154. HSPICE Signal Integrity Simulation (SIS) software now includes CosmosScope
155. Creation of an Equivalency Checking (EC) netlist for Formality
156. Formality now supports RAM inferencing
157. Formality now supports multiplier matching
158. Formality now supports verification for operands greater than 18 bits.
159. Added over 40 new rules to LEDA HDL analyzer (now has ~ 130 FPGA-specific rules)
160. Creation of an Equivalency Checking (EC) netlist for Verplex Conformal
161. Verplex now supports multiplier matching
162. Verplex now supports verification for operands greater than 18 bits
163. Cadence NCsim simulation speed improvements
164. Enhanced simulation library compilation support
165. Ability to simulate structural HDL netlists without requiring SDF
166. Enhancements to security attributes used in netlists containing IP cores
167. Ngd2hdl executable created to create VHDL and Verilog simulation models from CoreGen
168. Support CoolRunner II Dual Edge Triggered flip-flops in Synplicity & Leonardo Spectrum

Incremental Design

169. Simplified PAR guide report tells whether module was guided or not
170. Incremental Enabled mode preserves module boundaries even if not registered
171. MAP tells PAR which modules are identified as changed
172. Improved MAP report to identify changed modules.

Constraints Editor

173. New dialog graphics added to show example circuits and timing diagrams.
174. Associates PERIOD clock edge with OFFSET values.
175. Support for Source Synchronous input timing
176. Improved help for constraining methodology
177. Input Jitter added to PERIOD dialog
178. Apply buttons added to all applicable dialogs
179. Support for creating XCF timing constraints file for XST
180. New dialog for creating falling/rising edge groups. Assists in DDR timing.

iMPACT

181. New archiving capability.
182. Improved progress bar calibration, and other visual run-time clues
183. Support Auto-Insertion of Signature specified in JEDEC file
184. Link to Web-Based configuration troubleshooter URL
185. Ability to create a 'C' language or custom formatted version of the PROM file
186. Wizards start at the appropriate point in the wizard dialogs
187. Improved wizard so that it does not clean everything on modes that are not being used
188. Save equivalent batch mode command history in separate file.
189. Ability to create and execute Xilinx Serial Vector Format (XSVF) files
190. Support for revisioning in the forthcoming Xilinx XCF08P, XCF16P, and XCF32P PROMs
191. Improved Boundary-Scan chain debugging

Architecture Wizard

192. New flows, including Board Deskew, Clock Forwarding, Clock Switching, and Cascading in Series
193. Phase Shift value now shown in degrees
194. Advanced setup includes insertion of reset logic for external feedback
195. Support for 10 Gbps transceivers
196. Improved channel bonding support for up to 24 transceivers
197. Automatic placement of channel bonded transceivers

CoreGen

198. Greatly improved ProjNav integration
199. Memory editor reads Excel files
200. Generates UNISIM level HDL models for some cores
201. Faster loading of core repository, visual progress bar
202. GUI indicators for core license status

ECS

203. Can now Generate HDL Template from the selected symbol
204. Bustaps are automatically created when a wire is drawn between a bus and a pin
205. Quick I/O Marker automatically adds a short wire and I/O Marker of the correct direction to each pin
206. A group of selected Instances or I/O Markers can be aligned using the Align command.
207. The Last/Next View feature allows previously used viewpoints/zoom levels to be recalled
208. Autoscrolling feature causes the viewpoint to automatically scroll when the user drags
209. The "hot zone" size and scrolling speed can be adjusted via the Preferences dialog.
210. Snap To feature for I/O
211. Text Alignment command allows a group of selected text items to be as appropriate
212. Symbol Info command will display a data sheet for the currently selected
213. When moving a visible attribute, a line is drawn to the corresponding instance's origin
214. Miscellaneous DRC improvements
215. Rename Selected Instance makes renaming objects easier.
216. Select button has been added to Find dialog, allowing found item(s) to be selected directly
217. When a pin is added in the symbol editor, an attribute is automatically added

RTL Viewer

218. The Viewer can now flatten sub-modules to show their contents
219. The size of modules that should be flattened is selectable
220. The user can now cross-probe from RTL instances to the corresponding HDL line numbers
221. Support for incremental synthesis has been added
222. Instance and Symbol names can now be added to RTL Views
223. Finite State Machine symbol support has been added
224. Multiple-bit In/Out ports on instances are now notated with their width
225. Double-clicking an object in the Hierarchy View causes that object's underlying schematic to be generated

XPower

226. Improved accuracy for I/O Power - Each voltage source used represented in the summary
227. Improved accuracy of special blocks: BRAM, MULT18X18, PPC, MGT, DCI I/Os
228. Separate temperature grades - commercial, industrial and automotive
229. Re-write of XPower GUI in C++ provides an average of 2X runtime improvement
230. Worst Case Power and Thermal reporting based on conditions specified by the user
231. Extra fields in the thermal tab for FPGA designs
232. Maximum ambient temperature, Junction temperature for worst-case reporting
233. New XAD file format to replace the VCD file. Reduced loading from hours to minutes

Data2mem

234. Support for external memory
235. Added option to create an output log file
236. Data2mem accessible within IMPACT

General

237. Support for Native Redhat Linux
238. Support for additional Spartan-3 devices
239. Explicit support for military and industrial families
240. Support for Japanese, Korean and Chinese Windows in initial ISE release
241. New version of MXE: 5.7c

ChipScope Pro

242. Added Solaris support
243. Added 16 state FSM trigger function
244. Enhanced Trigger Output functionality
245. Support for new core features
246. Dynamic core status reporting
247. Drag and drop signals / buses into viewers
248. Color coding for signals / buses
249. Time units shown on the ruler
250. Improved signal browser functionality
251. Enhanced bus manipulation features

CPLD

252. Integrate static timing report into HTML report (new format)
253. Integrate HTML report into project navigators embeded browser
254. Improve the equation format for readability.
255. Improved partial fit report for usability.
256. Enhance Error/Warning/Information messages
257. Enhance Graphical Views and web graphics.
258. Improve the autofit device selection algorithm to provide a tighter fit when possible.
259. Enhancement to use smaller device with larger package in auto device selection
260. Preserve bus ordering through the fitter and timing simulation
261. Integration of CPLDfit and Tsim into the ISE database

Netgen

262. Combined ngdanno, ngd2ver and ngd2vhd to create the new Netgen program
263. Better support for creation of netlists for third party static timing analyzers and equivalency checkers
264. Timing simulation netlists match original design hierarchy for easier verification and simulation
265. Ability to simulate structural HDL netlists without requiring SDF
266. Enhancements to security attributes used in netlists containing IP cores

Install

267. Make installer bilingual (Japanese and English)
268. Provide capability to install smartmodels
269. Install cable drivers when doing a network install
270. Provide uninstall functionality with network install