Glossary of Terms

Definitions for common terms on Xilinx.com

Browse the glossary, or choose one of the following terms:

ASIC

Application Specific Integrated Circuit. A custom chip that uses fixed logic.

Assembly Site

Package materials vary by supplier. In some cases Xilinx utilizes multiple suppliers, therefore where applicable, material sets are listed for each. To identify the applicable information for your device, refer to the top mark located on the physical package. This information is also broken out in the Material Data Declaration Data Sheet (MDDS).

    Assy A: “A” or “F” digit located as first character in fourth line of package top mark
    Assy R: “R” digit contained in third line of package top mark. (For example, VQ44ART0233).
    Assy D: “D” digit located as first character in fourth linke of package top mark.

Compatibility with SnPb Solder

See Application Note XAPP427 Implementation and Solder Reflow Guidelines for Pb-Free Packages for more information.

Cores

In the semiconductor design industry, refers to predefined functions such as processors or bus interfaces that are typically licensed from the software developer. Cores can be implemented directly in silicon, either in fixed logic or programmable logic devices, and saves chip designers time during product development. Synonymous with Intellectual Property.

CPLD

A Complex Programmable Logic Device. Logic densities usually less than 10,000 gates.

DSP

Digital Signal Processing. Can take place in dedicated DSP processors, fixed logic ASICs, or programmable logic devices. Some of the highest performing DSP systems are implemented in FPGAs because processing can be done on the chips in a parallel fashion.

Design Entry

The methodology designers use to create a chip, for example, schematic or hardware definition language.

EDA

Electronic Design Automation. Refers to a broad array of front-end (design entry) and backend (implementation) software tools used to create, simulate, verify and test the circuitry in chips.

Fabless

A semiconductor company that does not own or operate its own silicon wafer fabrication foundries but instead outsources manufacturing.

Fibre Channel

A high-bandwidth serial standard offering 1.06 Gbit/second transfer rates scalable to 2.12 or 4.24 Gbit/second. Capable of carrying multiple existing interface command sets, including Internet Protocol (IP), SCSI, IPI, HIPPI-FP, and audio/video.

FPGA

Field Programmable Gate Array. Invented by Xilinx in 1984. Gate counts now in the millions, with high level of system functions - processors, delay lock loops, clock managers, memory, serial transceivers -- integrated on a single FPGA chip.

InfiniBand

A new industry I/O specification using a 2.5 Gbit/seceond wire speed connection with one, four or twelve wire link widths. Applications include remote storage devices and servers.

Interconnect

In programmable logic, silicon devoted to connecting memory elements on the chip to create a logic circuit.

I/O

Input/output. The physical connections, and the various electrical standards, for getting signals on and off a chip.

IP

Intellectual property. In the semiconductor design industry, refers to predefined functions such as processors or bus interfaces that are typically licensed from the software developer. IP can be implemented directly in silicon, either in fixed logic or programmable logic devices, and saves chip designers time during product development. Synonymous with Cores.

LDT

Lightning Data Transport, a chip-to-chip interconnect that provides a bandwidth from 6.4 Gb/sec per eight wire link width, and can support up to 32 links.

Lead / Ball Finish

Material composition of lead plating on lead frame packages and in the solder balls used on BGA packages. Material used for solder bump material in the flip chip package is also reported where applicable.

Pb = Lead, Sn = Tin, Ag = Silver. Numbers in front of chemical notations indicate percent of composition for the material which follows.

LUT

Look up table. When combined with one or more flip flops, constitutes the basic memory-based programmable logic element in FPGAs.

MAC

Multiply and accumulate. A measure of arithmetical performance in digital signal processing systems. FPGAs can achieve some of the highest DSP performance, calculating a half trillion MACs per second.

Material Data Declaration Sheet (MDDS)

The MDDS template used by Xilinx is based on the Electronic Industries Alliance (EIA) September 19, Material Composition Declaration Guide dated September 19, 2003 for Level A and Level B materials of interest.

As per EIA, "Level A” List is composed of materials and substances subject to currently enacted legislation that:
a) Prohibits their use and/or marketing
b) Restricts their use and/or marketing
c) Requires reporting or results in other regulatory effect.

As per EIA, "Level B” List is composed of materials and substances that the industry has determined relevant for disclosure because they meet one or more of the following criteria:
a) Precious materials/substances that provide economic value for end-of-life management purposes
b) Materials/substances that are of significant environmental, health, or safety interest
c) Materials/substances that would trigger hazardous waste management requirements
d) Materials/substances that could have a negative impact on end-of-life management.

See the EIA standard for more specific information.

Max Time within 5C of actual Peak Temperature

Information listed is per the latest JEDEC standard

NRE

Non-recurring Engineering. In the world of fixed logic chip design, refers to the one-time, up front costs customers incur in designing a chip. Includes software tools, engineering time, design verification, mask sets and prototypes. In the programmable logic world, usually refers to the expenses associated with converting a PLD design to a fixed logic design to gain a cost reduction.

Package Designator

Materials listed are package related. To relate information to a specific device part number, refer to the package designator portion of the part number. For example: XC3S200-4TQ144C. The bold, underlined section represents the package designator. For Pb-free packages, an additional "G" is added to the package designator. For example: TQ144 (standard) would be TQG144 (Pb-free).

PAL

Programmable Array Logic. The earliest and, in terms of logic density, the simplest form of a programmable logic device.

Place and Route

Using backend implementation software tools, the process of connecting various memory elements in an FPGA to create a custom logic circuit.

Platform FPGA

Standard FPGAs that are targeted at multiple applications such as embedded processing, digital signal processing. Xilinx Virtex-II family was the first embodiment of Platform FPGAs.

PLD

Any programmable logic device. Encompasses PALs, SPLDs, CPLDs and FPGAs.

POS-PHY4

Also, PL4. A 13.3 Gbit/second parallel link layer to physical layer interface for packet and cell transfer over SONET for OC-192c and 10 G bit/second Ethernet applications. POS-PHY4 is a 16-bit point-to-point interconnect with 832 Mb/sec per bit signaling utilizing double data rate clocking.

Product Mass

The product mass represents an average weight in grams. Package weights will vary slightly based on the die used in the package.

Product Term

The basic memory-based programmable logic element in CPLDs.

Reconfigurable Computing

A methodology of using programmable logic devices in a system design such that the hardware-based logic can be changed to perform various tasks. Benefits includes the use of fewer components, less power, and the flexibility that bring about. Also allows networked equipment in the field to be upgraded or repaired remotely.

RapidIO

A next-generation switched-fabric interconnect architecture for embedded systems that is optimized for both high bandwidth and low latency. Initial implementations are expected to exceed 1.0 Gbit/second throughput based on clock rates from 250 MHz and higher. Applications will include embedded systems in the networking, multimedia, storage and signal-processing sectors.

RoHS Compatible

Xilinx defines RoHS to mean products that are compatible with the current RoHS requirements for all six substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, Xilinx Pb-free / RoHS products are suitable for use in specified Pb-free processes.

Tin (Sn) Whisker Mitigation

Xilinx believes the risk of Sn whisker is very low if the process is well controlled. Xilinx recommends annealing products that use Matte Sn plating on the leads for 1 hr @ 150 C. Xilinx has seen data that shows that anneal is an effective whisker mitigation method. Research shows that whisker is a result of stress build up in the plating. Anneal alleviates the stress in the plating by producing a uniform inter-metallic layer

XAUI

A quad transceiver utilizing 3.125 Gbit/second serial links to create a 10 gigabit attachment unit interface (XAUI). Multiple XAUI interfaces can be implemented to allow a single chip to interface to both 10 Gigabit Ethernet and OC-192c.