Xilinx Glossary

3G
Third Generation

3GPP
Third Generation Partnership Project

3-state buffer
A buffer that places an output signal in a high-impedance state to prevent it from contending with another output signal.

ACK
Acknowledgement

ACLR
Adjacent Carrier Leakage Ratio

ACP

1. Accelerator Coherency Port
2. Adjacent Channel Power

ADC
Analog-to-Digital Converter

address
The identification of a storage location, such as a register or a memory cell.

AER
Advanced Error Reporting

AFIR
Acceptance Filter ID Register

AFMR
Acceptance Filter Mask Register

AFR
Acceptance Filter Register

ALM
Alarm

ALU
See Arithmetic Logic Unit.

AMBA
Advanced Microcontroller Bus Architecture. An on-chip communications standard for high-performance 32–bit and 16–bit embedded microcontrollers.

AMP
Asymmetrical multiprocessing. Typically, the CPUs have separate operating systems, but share resources. Applies to Zynq-7000 All Programmable SoC.

AN
Autonegotiation

annotation
The insertion of simulation values into the schematic.

ANSI
American National Standards Institute

antifuse
A device in which connections are permanently programmed by burning out a fuse.

AOSR
Alarm Output Status Register

APB
Advanced Peripheral Bus

API
Applications Programming Interface. A set of software libraries, developed by a particular software vendor, that allows third party software programs to interface with programs from that vendor.

APP
Application

APU
Application Processor Unit

architecture
The common logic structure of a family of programmable integrated circuits. The same architecture can be realized in different manufacturing processes.

Architecture Wizard
A graphical application that allows you to customize Digital Clock Managers (DCMs) and serial transceivers. It generates HDL files for all supported synthesis tools. It also allows jitter calculation for DCMs and channel bonding for serial transceivers. This application is available from the Project Navigator.

ARD
Address Range Definition

area constraints
Area constraints are created by the user or a process such as synthesis to direct the optimization process that takes place during design implementation.

area-and-speed calculator
A process that provides information about the area versus speed trade-offs for a design. The synthesis tools use this information to estimate the trade-offs accurately.

ARHT
Auto Reload/Hold

arithmetic equations
Equations which specify the special arithmetic capabilities of the Xilinx® CPLDs.

Arithmetic Logic Unit (ALU)
A logic function that performs arithmetic computations, such as addition, multiplication, and comparison operations. The ALU is one component of the central processing unit (CPU).

ARM Processor
Advanced RISC Machine Processor. A 32–bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings.

ASIC
Application-Specific Integrated Circuit. An integrated circuit customized for a particular use (versus general-purpose use). For example, a chip designed solely to run a cell phone for a specific manufacturer is an ASIC. Either a full-custom circuit in which every mask is defined by the user, or a semi-custom circuit (gate array) where only a few masks are defined.

assembly site
Package materials vary by supplier. In some cases Xilinx utilizes multiple suppliers, therefore where applicable, material sets are listed for each. To identify the applicable information for your device, refer to the top mark located on the physical package. This information is also broken out in the Material Data Declaration Data Sheet (MDDS).

• Assy A: “A” or “F” digit located as first character in fourth line of package top mark
• Assy R: “R” digit contained in third line of package top mark. (For example, VQ44ART0233).
• Assy D: “D” digit located as first character in fourth line of package top mark.

assertion
A warning that is activated when a mismatch in the simulated and expected value occurs. User defined and automatic assertions are supported.

asynchronous debugging
A debugging mode in which data is captured independent of the system clock.

asynchronous logic
Logic which changes state independently of clock changes. A signal whose intended function is performed immediately when the signal is asserted without regard to a clock.

asynchronous register
A register whose state changes independently from the clock.

Asynchronous Transfer Mode (ATM)
A method of transmitting voice, data, and video in fixed-size packets over high-speed telecommunications channels.

ATM
See Asynchronous Transfer Mode.

attributes
Instructions placed on symbols or nets in an FPGA or CPLD schematic to indicate their placement, implementation, naming, direction, or other properties.

AV
Audio Visual

AVB
Audio Video Bridging

AXI
Advanced eXtensible Interface protocol. A bus protocol that is targeted at high performance, high clock frequency system designs and includes a number of features that make it very suitable for high-speed sub-micron interconnect.

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back-annotation
Translation of a routed or fitted design to a timing simulation netlist.

BAR
Base Address Register

BBD File
Black Box Definition file. The BBD file lists the netlist files used by a peripheral.

BBRAM
Battery-Backed RAM

BBU
Baseband Units

BCH
Broadcast Channel

BCR
Bridge Control Register

BE
Byte Enable

behavior
A set of sequential statements specified within a process statement.

behavioral design
A technology-independent, text-based design that incorporates high-level functionality and high-level information flow.

behavioral design method
A method of defining a circuit in terms of a textual language rather than a schematic of interconnected symbols.

behavioral simulation
Behavioral simulation is usually performed on designs that are entered using a hardware description language (HDL). This type of simulation takes place during the pre-synthesis stage of HDL design. Functional simulation checks that the HDL code describes the desired design behavior. Behavioral simulation is a simulation process that is performed by interpreting the equations that define the design. The equations do not need to be converted to the logic that represents them.

BEL Placement Constraint
Basic Element (BEL) constraints can be assigned to the leaf-level instances that have placement sites assigned to specific logic device gates. Assigning a BEL constraint results in an LOC and a BEL constraint being “fixed” and written in the exported UCF files for the instance. Depending on the zoom level, these LOCs appear in the Device view either as rectangles within their respective assigned Sites or as logic functions symbols within the site.

BFL
Bus Functional Language.

BFM
Bus Functional Model

BFN
B Frame Number

BIER
Bridge Interrupt Enable Register

binary counter
A counter implemented in base 2.

binary encoding
Binary or maximal encoding is a type of state machine encoding that uses the minimum number of registers to encode the machine. Each register is used to its maximum capability.

BIR
Bridge Interrupt Register

BIT file
A bitstream file.

Bitgen
A program that produces a bitstream for Xilinx device configuration. BitGen takes a fully routed native circuit description (NCD) file as its input and produces a configuration bitstream, a binary file with a .bit extension.

BitInit
The Bitstream Initializer tool. Initializes the instruction memory of processors on the FPGA and stores the instruction memory in FPGA block RAMs.

bitstream
A bitstream is a stream of data that contains location information for logic on a device, that is, the placement of configurable logic blocks (CLBs), input/output blocks (IOBs), 3-state buffer (TBUFs), pins, and routing elements. The bitstream also includes empty placeholders that are filled with the logical states sent by the device during a readback. Only the memory elements, such as flip-flops, RAMs, and CLB outputs, are mapped to these placeholders, because their contents are likely to change from one state to another. When downloaded to a device, a bitstream configures the logic of a device and programs the device so that the states of that device can be read back. A bitstream file has a .bit extension.

block

1. A group of one or more logic functions.
2. A schematic or symbol sheet. There are four types of blocks:
   • A Composite block indicates that the design is hierarchical. A composite block is a symbol representing an underlying schematic or netlist.
   • A Module block is a symbol with no underlying schematic. A module block is also referred to as a primitive.
   • A Pin block represents a schematic pin.
   • An Annotate block is a symbol without electrical connectivity that is used only for documentation and graphics.

block RAM
A block of random access memory built into a device, as distinguished from distributed, LUT-based random access memory.

BMCA
Best Master Clock Algorithm

BMM File
A Block RAM Memory Map (BMM) file is a text file that has syntactic descriptions of how individual block RAMs constitute a contiguous logical data space. Data2MEM uses BMM files to direct the translation of data into the proper initialization form. Since a BMM file is a text file, it is directly editable.

bottom-up design
An HDL design methodology where already defined HDL blocks are merged into one overall desired design behavior. The lowest level portion of your design is completed first. Only after the low-level building blocks are complete do you finish higher-level hierarchical blocks in your design. This methodology is typically used with schematic capture programs.

boundary-scan
A method used for board-level testing of electronic assemblies. The primary objectives are the testing of chip I/O signals and the interconnections between ICs. Boundary-scan is the method for observing and controlling all new chip I/O signals through a standard interface called a Test Access Port (TAP). The boundary-scan architecture includes four dedicated I/O pins for control and is described in IEEE spec 1149.1.

breakpoint
A condition for which a simulator must stop to perform simulation commands.

BRG
Baud Rate Generator

BRPR
Baud Rate Prescaler

BRR
Buffer Ready Register

BSB
Base System Builder. A wizard for creating a complete design in Xilinx® Platform Studio (XPS). BSB is also the file type used in the Base System Builder.

BSP
Board Support Package / Bitstream Processor

BTL
Bit Timing Logic

BTR
Bit Timing Register

BTS
Base Transceiver Station

BTT
Bytes to Transfer

buffer
An element used to increase the current or drive of a weak signal and, consequently, increase the fanout of the signal. A storage element.

BUFG
Global Buffer (Xilinx® FPGA component)

BUFT
A 3-state buffer.

byte-wide PROM
A programmable read-only memory (PROM) which supplies data one byte at a time.

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C2P
See clock-to-pad path.

C2S
See clock-to-setup path.

CA
Completer Abort

CAE
Computer Aided Engineering. The original term for electronic design automation (EDA). Now, often refers to the software tools used to develop the manufacturing tooling for the production of electronic system such as for the panelization of circuit boards.

CAE tool
A Computer-Aided Engineering (CAE) tool. Usually refers to programs such as Innoveda, Cadence, or Mentor Graphics that perform design entry and design verification.

CAN
Controller Area Network

CAPEX
Capital Expenditure

carry
A quantity that is transferred in addition and subtraction from one number to the next one of higher place value.

carry logic
Logic that is designed to speed up and reduce the area of counters, adders, incrementers, decrementers, comparators, and subtractors. It is a special interconnect that speeds up the carry path of adders and counters from one CLB to another. This dedicated carry line runs along each column of CLBs as well as the top and bottom CLBs.

carry-logic modes
The 43 specific carry-logic functions, such as decrement and increment, available in each CLB configuration.

carry look-ahead
A mechanism that enables the carries to be simultaneously applied to the sum bits in a parallel adder.

carry path
The computation of the carries in addition or subtraction from one CLB to another.

carry propagation time
The time it takes for a carry signal to traverse through the levels of component gates.

cascade
A circuit which connects the inputs of a module to the outputs of another.

CDC
clock-domain-crossing

CDMA
Central Direct Memory Access

CDMA
Code-Division Multiple Access

CDRSX
Common Digital Radio System — Xilinx® Edition

CE
Chip Enable / Clock Enable

cell
A hierarchical description of an FPGA.

Cfg
Config

CFI

1. Common Flash Interface
2. Control Format Indicator (LTE)

CFR
Crest Factor Reduction

checksum
A summation of bits or digits generated according to an arbitrary formula used for checking data integrity. To verify that the data represented by a checksum number has been entered correctly, verify that the checksum number generated after processing is the same as the initial number.

CIB
See component interface browser.

CLB
Configurable Logic Block. The basic FPGA cell. A CLB includes function generators (lookup tables, or LUTs), registers (flip-flops or latches), and reprogrammable routing controls (multiplexers). CLBs implement macros and other designed functions. They provide the physical support for an implemented and downloaded design. CLBs have inputs on each side, and this versatility makes them flexible for the mapping and partitioning of logic.

clear preset
A synchronous reset.

clock
A signal that represents the time that a wave stays at a High or Low state. The rising and falling edges of a clock square wave trigger the activity of the circuits.

clock buffer
A circuit element used to increase the current or drive of a weak clock signal and consequently increase its fanout.

clock enable
A binary signal that allows or disallows synchronous logic to change with a clock signal. When enabled, this control signal permits a device to be clocked and to become active.

clock input path
A path which starts at either an input of the chip or at the output of a flip-flop, latch, or RAM and ends at any clock pin on a flip-flop or latch enable. The clock input path time is the maximum time required for the signal to arrive at the flip-flop clock input. Clock input paths help to determine system-level design timing.

clock period
The time required for a periodic waveform to repeat itself.

clock skew
The time differential between two or more destination pins in a path.

clock-to-pad path (C2P)
A path which starts at the Q output of a flip-flop or latch and ends at an output of the chip. It includes the clock-to-Q delay of the flip-flop and the path delay from that flip-flop to the chip output. The clock-to-pad path time is the maximum time required for the data to leave the source flip-flop, travel through logic and routing, and arrive at the output before the next clock edge occurs.

clock-to-setup path (C2S)
A path which starts at the Q output of a flip-flop or latch and ends at an input to another flip-flop, latch, or RAM, where that pin has a setup requirement before a clocking signal. It includes the clock-to-Q delay of a flip-flop, the path delay from that flip-flop to the next flip-flop, and the setup requirement of the next flip-flop. The clock-to-setup path time is the maximum time required for the data to propagate through the source flip-flop, travel through the logic and routing, and arrive at the destination before the next clock edge occurs.

CML
Current Mode Logic

CMOS
Complementary Metal Oxide Semiconductor. An advanced IC manufacturing process technology characterized by high integration, low cost, low power, and high performance.

CMOS transistors
CMOS transistors are used in Programmable Interconnect Points (PIPs) and switching matrices.

CMP
Configured Maximum Power

CMT
Clock Management Tile

combinatorial input
Combinatorial input is the combination of a pad primitive and a function primitive.

combinatorial logic
Logic that has no storage capacity, that is, not controlled by a clock (asynchronous). For example, logic gates.

command file
In simulation, a command file is a file containing a list of commands that assign vectors, generate input waveforms and clocks, and display signals. It is submitted for execution during simulation. You can create a command file with a text editor or from a set of input waveforms.

compiler
A language interpreter. The compiler interprets HDL and makes concurrent process implementations for target architectures.

complexity
The number of gates on a device.

component
A logical configuration that, at some point, goes into a physical site. Examples of components are CLBs, IOBs, 3-state buffers, pull-up resistors, and oscillators. Components are comprised of BELs. A slice is one example of a component. The component is the unit of granularity for placement and routing in the FPGA Editor. Also the component is the level at which device timing is characterized.

component interface
A description of how a Mentor Graphics component interfaces with upper-level hierarchy. A port description with a model registry, roughly equivalent to an entity port listing (along with architecture declarations) in VHDL.

component interface browser (CIB)
A program that allows a designer to view and edit a component interface. In most cases, this is done to add or remove models from a component's model registry.

configuration
The process of loading design-specific bitstreams into one or more devices to define the functional operation of the logical blocks, their interconnections, and the chip I/O.

configuration file
A file that contains the bitstream used to program an FPGA device or PROM. The format of that file can be binary (.bit) or ASCII format (.mcs or .rst).

configuration modes
Configuration modes are the modes available on the Xilinx configuration cables. They include JTAG, SelectMAP, and Slave Serial.

configuration pins
Pins that are used to load design-specific programming data into one or more logic blocks to define the functional operation of a device's internal blocks and interconnections.

Configuration Space
One of the four address spaces within the PCI EXPRESS® architecture (the others are I/O, memory, and message). Packets with a Configuration Space address are used to configure a device.

console log
A record of the commands that you invoked during a session.

Constraint Set
A constraint set is one or more constraint files used for analysis and implementation purposes. They are managed within the Sources view in the PlanAhead™ software. Different constraint sets can be used to experiment with constraints or to explore different devices.

constraints
Specifications for the implementation process. There are several categories of constraints: routing, timing, area, mapping, and placement constraints. Using attributes, you can force the placement of logic (macros) in CLBs, the location of CLBs on the chip, and the maximum delay between flip-flops. PAR does not attempt to change the location of constrained logic.

Constraints Editor
Xilinx software that allows you to enter timing constraints and pin location constraints. The user interface simplifies constraint entry by guiding you through constraint creation without your needing to understand UCF file syntax.

constraints file
A file which specifies constraints (location and path delay) information in a textual form. An alternate method is to place constraints on a schematic.

contention
The state in which multiple conflicting outputs drive the same net.

CONVSTR
CONVST Register

CORE Generator
Xilinx software tool that delivers parameterized cores optimized for Xilinx® FPGAs. The CORE Generator™ tool provides a catalog of ready-made functions ranging in complexity from simple arithmetic operators (such as adders, accumulators, and multipliers) to system-level building blocks (such as filters, transforms, FIFOs, and memories).

cores
In the semiconductor design industry, refers to predefined functions such as processors or bus interfaces that are typically licensed from the software developer. Cores can be implemented directly in silicon, either in fixed logic or programmable logic devices, and saves chip designers time during product development. Synonymous with Intellectual Property.

counter
A circuit, composed of registers, that counts pulses, often reacting or causing a reaction to a predetermined pulse or series of pulses. Also called a divider, sometimes accumulator.

CP
Cyclic Prefix

CPHA
Clock Phase

CPICH
Common Pilot Channel

Cpl
Completion

CplD
Completion with Data

CPLD
Complex Programmable Logic Device (CPLD). A single-chip logic solution. Logic densities usually less than 10,000 gates.

CPOL
Clock Polarity

CPRI
Common Packet Radio Interface

CPU
Central Processing Unit

CR
Control Register

CRC
Cyclic Redundancy Check

critical path
A signal in a section of combinatorial logic that limits the speed of the logic. Storage elements begin and end a critical path, which may include I/O pads.

cross probing
Interprocess communication between software tools.

CS
Chip Select

CSMA/CD
Carrier Sense Multiple Access with Collision Detection

CTI
Cross Trigger Interface

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DA
Destination Address

DAC
Digital-to-Analog Converter

daisy chain
A series of bitstream files concatenated in one file. It can be used to program several FPGAs connected in a daisy-chain board configuration.

dangling bus
A bus which connects to a component pin or net at one end and unconnects at the other. A small filled box at the end of the bus indicates a dangling bus.

dangling net
A net which connects to a component pin or net at one end and unconnects at the other. A small filled box at the end of the net indicates a dangling net.

DAP
Debug Access Port

data center
Servers, networking equipment, storage devices, and application-specific appliances that work together to provide the backbone of cloud computing.

Data Link Layer
The middle layer of the PCI EXPRESS® architecture between the Transaction Layer and the Physical Layer.

Data2Mem
This Xilinx program conveniently incorporates CPU software images into FPGA bitstreams, and executes that software from block RAM-built address space.

dataflow modeling
The use of concurrent signal assignment statements.

dB
decibel

dBc
decibel relative to carrier

dBFS
decibel relative to digital full-scale

dBm
decibel relative to one milliwatt

DCH
Dedicated Transport Channel

DCI
Downlink Control Information

DCL
Dynamic Control Layer

DCM
Digital Clock Manager. A design element which provides multiple functions. It can implement a clock delay locked loop, a digital frequency synthesizer, digital phase shifter, and a digital spread spectrum.

DCR
Device Control Register

DDAR
DMA Destination Address Register

DDR
Double Data Rate

DDRC
Double data rate DRAM memory controller.

debugging
The process of reading back or probing the states of a configured device to ensure that the device is behaving as expected while in circuit.

DECERR
Decoder Error status in AXI4. See also: MDE.

declared signal
These signals are not input or output signals. They are internal signals within the device.

decoder
A circuit that translates n input lines of binary information into 2ⁿ output lines. It is the opposite of an encoder.

Delay Locked Loop (DLL)
A digital circuit used to perform clock management functions on- and off-chip.

density
The number of gates on a device.

Design
A design is defined as a netlist (elaborated RTL or synthesized), a constraint set, and a target device. You do not need to create designs to use the PlanAhead™ software. Designs are stored in memory during the PlanAhead current session only, and are used to analyze the design snapshot and to launch Runs. Implementation runs can be launched using any external User Constraints File (UCF). Each project netlist can support multiple designs using different constraints or devices.

design entry
The methodology designers use to create a chip, for example, schematic or hardware definition language.

design implementation
The design implementation specification refers to the actual implementation of the design from low-level components expressed in bits. This is different from the functional specification of the design, which refers to the definition of the design or circuit function.

design rule check
A Design Rule Check (DRC) is a series of tests that discovers logical and physical errors in the design.

design specification
The top-level of a design used to define its function. The specifications function is created in terms of behavioral or structural primitives. The two methods of entering a design are graphical descriptions (schematics) and textual descriptions (HDL).

destination
A sink node or stopping point for a timing analysis path. The data input of a synchronous element or a pad.

DEVC
Device Configuration Unit

device
A device is an integrated circuit or other solid-state circuit formed in semiconducting materials during manufacturing. Each Xilinx architecture family contains specific devices.

device model
A VHDL description of the internal and external views of a digital device, including the structure and the communication interface of the device with its environment.

DFE
Decision Feedback Equalizer

DGIER
Device Global Interrupt Enable Register

DIC
Deficit Idle Count

differential pairs
Differential pairs are identical to LVDS (Low Voltage Differential Signal) and LVPECL signals. Some devices incorporate differential signaling. Two pins are utilized for these signals to be connected to the device. These are known as differential pin pairs. Each differential pin pair has a positive (P) and a negative (N) pin. I/O pins for differential signals can either be synchronous or asynchronous, input or output. The pin pairs can be used for synchronous input and output signals as well as asynchronous input signals. However, only some of the differential pairs can be used for asynchronous output signals. Differential signals require the pins of a pair to switch almost simultaneously. If the signals driving the pins are from IOB flip-flops, they are synchronous. If the signals driving the pins are from internal logic, they are asynchronous.

DIN pin
An FPGA pin that loads a bitstream in serial mode.

direct interconnect
A net that aligns the carry with the CLB rows and columns, propagating and connecting the carry to the flip-flops of a counter.

DISR
Device Interrupt Status Register

distributed RAM
Random Access Memory (RAM) that is distributed throughout the programmable logic in the CLBs. Distributed RAM can be used to change the address values of the function generator (lookup table, or LUT) of which it is a part.

distributed ROM
Read Only Memory (ROM) that is distributed throughout the programmable logic in the CLBs.

DLC
Data Length Code

DLL
See Delay Locked Loop.

DLLP
Data Link Layer Packet

DLMB
Data-side Local Memory Bus

DL-SCH
Downlink Shared Channel

DMA
Direct Memory Access

DMAC
Direct Memory Access Controller

DMACR
DMA Control Register

DMALR
DMA Length Register

DMASR
DMA Status Register

don't care
The value of a variable when that value has no effect on the output. Don't-care values are represented by an X in truth tables.

DOPB
Data-side On-chip Peripheral Bus

double-length line
An interconnect line that is switched only every other switch matrix.

downloading
Downloading is the process of configuring or programming a device by sending data to the device.

DPCH
Dedicated Physical Channel

DPRAM
Dual Port Random Access Memory

DRAM
Dynamic Random Access Memory

drawn width
The machine-calibrated gate width.

DRC
Design Rule Check. A program that checks the NCD file for design implementations for errors.

DRE
Data Realignment Engine

DRP
Dynamic Reconfiguration Port

DRR
Data Receive Register

DSAR
DMA Source Address Register

DSN
Device Serial Number

DSP
Digital Signal Processing. A specialized microprocessor with an optimized architecture for high-speed processing of large amounts of digital information. Used in audio, communications, image manipulation, and other data-acquisition and data-control applications. Can take place in dedicated DSP processors, fixed logic ASICs, or programmable logic devices. Some of the highest performing DSP systems are implemented in FPGAs because processing can be done on the chips in a parallel fashion.

DSPLB
Data-side Processor Local Bus

DSRR
DMA Software Reset Register

DTE
Data Terminal Equipment

DTR
Data Transmit Register

DUC
Digital Up Conversion

DUT
Device Under Test

duty cycle
In digital electronics, this term describes the percentage that a digital signal is High during one cycle. For example, a 60% duty cycle means that the voltage is High (logical 1) for 60% of the cycle, which means that the voltage is Low for 40% of the cycle.

DVE
Discovery Visualization Environment

DW, DWORD
Double Word. Four bytes.

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ECAM
Enhanced Configuration Access Mechanism

ECC
Error Correction Code. Additional circuitry added to an instance of a block RAM to correct single bit failures during access. While associated with a block RAM, the ability to turn ON/OFF this implementation is via the block RAM Controller that is the interface between the block RAM and the processor(s).

ECR
Error Counter Register

ECRC
End-to-End CRC

EDA
Electronic Design Automation. Refers to a broad array of front-end (design entry) and back-end (implementation) software tools used to create, simulate, verify and test the circuitry in chips.

edge decoder
A decoder whose placement is constrained to precise positions within a side of the FPGA.

EDIF
Electronic Data Interchange Format. An industry standard file format for specifying a design netlist.

editor
A tool that allows you to view or modify an ASCII file.

EDK
Xilinx® Embedded Development Kit (EDK).

EEPROM
Electrically Erasable Programmable Read-Only Memory. A variety of EPROM that can be erased electrically. See also: EPROM.

effective width
The actual gate width after diffusion.

effort level
Effort level refers to how hard the Xilinx® Design System (XDS) tries to place or route a design. The effort level settings are as follows:

• High, which provides the highest quality placement but requires the longest execution time. Use high effort on designs that do not route or do not meet your performance requirements.
• Standard, which is the default effort level, provides a lower quality placement but requires the shortest execution time.

ELF File
Executable and Linkable Format file.

EMAC
Ethernet MAC

EMC
External Memory Controller

EMIO
Extended Multiuse I/O

enable input
A binary input that controls whether an output is enabled or disabled.

encoded state machine
A state machine which requires that you define the value of the state register for each state in the state table.

encoder
A symbol that translates 2ⁿ input lines of binary information into n output lines. It is the opposite of a decoder.

encoding
The data encoding scheme used for a design. Some examples of encoding types are unsigned binary, two's complement, and one-hot.

endpoint (EP)
A node which acts as either the driver to begin a path or a load to end a path.

entity
A set of interconnected components.

EOC
End of Conversion

EOF
End of Frame

EOP
End of Packet

EOS
End of Sequence

EP
See endpoint.

EP
Error Poison

EPP
Extensible Processing Platform

EPROM
An erasable PROM, which can be reprogrammed many times. Previous programs are simply erased by exposing the chip to ultra-violet light. See also: EEPROM.

equation splitting
An automatic process performed by CPLDs to divide large behavioral equations into smaller functions that fit within the available device macrocell resources.

equations files
Files that are used in behavioral designs.

ESR
Error Status Register

EXORmacs
EXORmacs is a Motorola PROM format supported by the Xilinx tools. Its maximum address is 16 777 216. This format supports PROM files of up to (8 x 16 777 216) = 134 217 728 bits.

external clock
The external clock is the system clock that is used from the target board during synchronous mode debugging. To use an external clock, connect the system clock to the CLKI pin and connect the download cable CLKO pin to the system clock loads.

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fabless
A class of semiconductor companies that design, test, market, and sell ICs, but subcontract the fabrication or 'fab' of semiconductor devices to a specialized manufacturer.

FAE
Field Application Engineer

fan-in
The number of parallel inputs a chip can absorb.

fan-out
The maximum number of specified unit loads that a specified output can drive.

fast carry
Arithmetic carry functions that use the dedicated fast carry chain that interconnects macrocells (CPLDs) or CLBs (FPGAs). These signals do not pass through the universal interconnect matrix universal interconnect matrix (UIM).

fast function block (FFB)
A group of macrocells in a CPLD that can process very high-speed logic.

fast output enable (FOE)
A 3-state control signal that uses the dedicated FOE wiring of the device, not the universal interconnect matrix (UIM) wiring.

FastCLK
A clock signal that uses the dedicated FastCLK wiring of the device, and not the universal interconnect matrix (UIM).

FastInput
An input to the device that connects directly to the function block inputs, bypassing the universal interconnect matrix (UIM).

FATfs
See XilFATfs.

FCB
Frame Clock Burst

FCS
Frame Check Sequence

FDM
Frequency Division Multiplexed

FEC
Forward Error Correction

F/F
Flip-Flop

FFB
See fast function block.

FFT
Fast Fourier Transform

Fibre Channel
A high-bandwidth serial standard offering 1.06 Gbit/second transfer rates scalable to 2.12 or 4.24 Gbit/second. Capable of carrying multiple existing interface command sets, including Internet Protocol (IP), SCSI, IPI, HIPPI-FP, and audio/video.

FIFO
First In, First Out

FIR
Finite Impulse Response

fitter
Software that maps a PLD logic description into the target CPLD.

fitting
The process of putting logic from your design into physical macrocell locations in the CPLD. Routing is performed automatically.

flat design
A flat design is a design composed of multiple sheets at the top-level schematic.

Flat View
In XPS, Flat view is available for both the IP Catalog and System Assembly Panels. In flat view, information in the Name column is directly visible and is not organized in expandable lists.

flattening
The process of resolving all of the hierarchy references in a design. If a design contains several instantiations of a logic module, the flattened version of that design duplicates the logic for each instantiation. A flattened design still contains hierarchical names for instances and nets.

floorplanning

1. The process of choosing the best grouping and connectivity of logic in a design.
2. The process of manually placing blocks of logic in an FPGA where the goal is to increase density, routability, or performance.

flow
An ordered sequence of processes that are executed to produce an implementation of a design.

FMAX
Maximum Frequency

FNR
Frame Number Register

FOE
See fast output enable.

footprint
The shape, pin names, and functionality of a library macro or component.

FPGA
Field Programmable Gate Array. A class of integrated circuits pioneered by Xilinx in 1984. An integrated circuit device or 'programmable platform' that can be programmed in the field after being manufactured, providing electronic product manufacturers with additional design flexibility. Unlike application-specific chips, FPGAs allow engineers to make changes very late in the design cycle and even upgrade products with new functionality after manufacture

FPGA Compiler
A Synopsys product which constrains and synthesizes an FPGA.

FPGA Editor
A graphical application for displaying and configuring Field Programmable Gate Arrays (FPGAs). The FPGA Editor requires a Native Circuit Description (.ncd) file. This file contains the logic of your design mapped to components (such as CLBs and IOBs). In addition, the FPGA Editor reads from and writes to a Physical Constraints File (PCF).

frequency
Frequency, IC design speed, is defined by the longest path delay in a circuit from a synchronous element to another synchronous element.

FROM:TO timespecs
A style of specifying timing which allows point-to-point, group-to-group, one-to-many, and many-to-one path types to be specified.

FSL
Fast Simplex Link. Unidirectional point-to-point data streaming interfaces ideal for hardware acceleration. The MicroBlaze™ processor has FSL interfaces directly to the processor.

function block
The high-density function block of the device, designed to provide the maximum logic density and containing several macrocells. The output pins associated with function blocks have the standard current drive capability.

function generator
A look-up table or black box with three or four inputs implementing any combinational functions of (2²)² or 256 functions or (2²)⁴ or 65556 functions. The output is any value resulting from the logical functions executed within the box. The function generator implements a complete truth table, allowing speedy prediction of the output.

functional simulation
The process of identifying logic errors in your design before it is implemented in a Xilinx device. Because timing information for the design is not available, the simulator tests the logic in the design using unit delays. Functional simulation is usually performed at the early stages of the design process.

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gate array
Part of an ASIC chip. A gate array represents a certain type of gate repeated all over a VLSI-type chip. This type of logic requires the use of masks to program the connections between the blocks of gates.

GBIC
Gigabit Interface Converter

Gb/s
Gigabits per second

GCC
GNU Compiler Collection

GEM
Gigabit Ethernet Media

GEMAC
Gigabit Ethernet Media Access Controller

generics
In VHDL, generics are used to pass certain types of information into a design description from their original environment.

GFC
Gigabit Fibre Channel

GIC
General Interrupt Controller

GIE
Global Interrupt Enable register

GIER
Global Interrupt Enable Register

Glitch
A false or spurious electronic signal or other anomalous behavior in hardware. A glitch might also describe something you see in software that is caused by hardware. The term should not be used to describe software errors. That is, it is not a synonym for bug. Correct usage: When you press the Sine Wave Sequencer button on the board, you might observe a sine wave glitch in the ChipScope™ Analyzer Waveform display window.

global 3-state net
A global 3-state net forces all device outputs to high-impedance state unless boundary scan is enabled and executes an EXTEST instruction.

global buffers
Low-skew, high-speed buffers that connect to long lines. They do not map logic. There is one BUFGP and one BUFGS in each corner of the chip. Primary buffers must be driven by an IOB. Secondary buffers can be driven by internal logic or IOBs.

global Set/Reset net
A high-speed, no-skew dedicated net, which reduces delays and routing congestion. This net accesses all flip-flops on the chip and can re-initialize all CLBs and IOBs.

GMII
Gigabit Media Independent Interface

GP
General Purpose

GPIO
General Purpose Input and Output. A 32-bit peripheral that attaches to the Processor Local Bus (PLB). There can also be GPIO pins, which don't have specific functions assigned to them. The designer can use them for design-specific functions.

GPP
General Purpose Processor

Gray Code
A type of binary code that represents numeric values in binary digits that differ from preceding digits in one place only. For example, in Gray code the integer 7 is implemented as 0100 and the integer 8 is implemented as 1100, instead of the binary representation of 0111 and 1000, respectively.

grey box methodology
Open box methodology uses Xilinx® design system (XDS) interactively for the implementation process. It is traditionally referred to as the "manual flow."

ground bounce
The occurrence of voltage spikes on the ground or power levels inside a chip primarily due to current changes in the combined inductance of ground pins, bond wires, and ground metalization. This problem frequently occurs when multiple outputs change state simultaneously.

group
A collection of common signals to form a bus. In the case of a counter, for example, the different signals that produce the actual counter values can be combined to form an alias, or group.

GSM
Global System for Mobile Communications

GT
GigaTransfers

GT/s
GigaTransfers per second

GUI
Graphical User Interface

guide file
A previously placed and routed NCD file that can be used in a subsequent place and route operation.

guide mode
Specifies an optional guide design file to be fed into the place and route process. The guide file is an NCD file that is used as a template for placing and routing the input design. This is useful if minor incremental changes have been made to create a new design.

guided design
The use of a previously implemented version of a file for design mapping, placement, and routing. Guided design allows logic to be modified or added to a design while preserving the layout and performance that have been previously achieved.

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hard macros
Macros created by the designer in the FPGA Editor and saved as NCD files. They can be instantiated in designs to maintain the exact placement and routing defined by the designer, but lack features for simulation and back-annotation since they do not have a corresponding logical representation in the design-capture netlist.

Hardware Description Language
A language that describes circuits in textual code. The two most widely accepted HDLs are VHDL and Verilog. HDL describes designs in a technology-independent manner using a high level of abstraction.

Hardware Platform
Xilinx® FPGA technology allows you to customize the hardware logic in your processor subsystem. Such customization is not possible using standard off-the-shelf microprocessor or controller chips. Hardware platform is a term that describes the flexible, embedded processing subsystem you are creating with Xilinx technology for your application needs.

hardwire
A non-reprogrammable device that has the same structure as an FPGA except that the memory cells and logic controlled are replaced by metal connections. This type of device is usually used after prototyping with an FPGA. It is used for high-volume designs.

HARQ
Hybrid Automatic Repeat ReQuest

HDFB
See high-density_function_block.

HDL
See Hardware Description Language.

HDLC
High-level Data Link Control

HEX
A simple text dump of the PROM data in HEX format. It has unlimited data capacity.

HI
HARQ Indicator

hierarchical design
A design description in multiple layers, from the highest (overview) to the lowest (circuit details). An alternative is flat design, where everything is described at the same level of detail.

Hierarchical View
In XPS, this is the default view for both the IP Catalog and System Assembly panel, grouped by IP instance. The IP instance ordering is based on classification (from top to bottom: processor, bus, bus bridge, peripheral, and general IP). IP instances of the same classification are ordered alphabetically by instance name. When grouped by IP, it is easier to identify all data relevant to an IP instance. This is especially useful when you add IP instances to your hardware platform.

high
In binary logic, there are two logic levels: High (1) and Low (0). The High condition represents the higher of two voltages.

high-density function block
A group of macrocells in a CPLD that can efficiently perform complex logic such as arithmetic operations.

high impedance
The third state or floating state of a 3-state component.

hold time
The amount of time required for a data input to be stable after the triggering edge of a clock to reliably activate the device.

Hot Plug
The ability to swap cards in a powered up system using software control.

Hot Swap
The ability to swap cards in a powered up system without software control.

HSDPA
High Speed Downlink Packet Access

HSEC
High-Speed Ethernet IP Core

HSTL
High-Speed Transceiver Logic

HWICAP
Hardware ICAP

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I/F
Interface

I/O
Input/Output. The physical connections, and the various electrical standards, for getting signals on and off a chip.

I/O banks
Groups of IOB blocks.

I/O blocks
The input/output logic of the device containing pin drivers, registers and latches, and 3-state control functions

I/O pads
Input/output pads that interface the design logic with the pins of the device.

I2C
Inter IC bus

IBA
Integrated Bus Analyzer

IBERT
Integrated Bit Error Ratio Test

IBIS
The Input/Output Buffer Information Specification. A device modeling standard. IBIS allows for the development of behavioral models used to describe the signal behavior of device interconnects.

IBISWriter
A Xilinx command line tool which outputs an .ibs file. This file consists of a list of pins used by a design; the signals internal to the device that connect to those pins; and the IBIS buffer models for the IOBs connected to the pins.

IBTTCC
Indeterminate Bytes to Transfer Command Calculator

IBUF
Input buffer. A circuit that acts as a protection for the chip, shielding it from eventual current overflows.

ICAP
Internal Configuration Access Port

ICR
Interrupt Clear Register

ID
Identifier

IDE
Integrated Development Environment

IDELAY
Input logic delay

IDR
Identifier of the Received Message

IDSEL
Initialization Device Select

IER
Interrupt Enable Register

IES
Incisive Enterprise Simulator

I/F
Interface

IFG
Interframe GAP

IIC
Inter-Integrated Circuit

IID
Interrupt ID

ILA
Initial Lane Alignment

ILA
Integrated Logic Analyzer

ILMB
Instruction-side Local Memory Bus

ILS
Initial Lane Synchronization

iMPACT
A Xilinx command line and GUI based tool that enables you to configure your PLD designs using Boundary-Scan mode. You can use iMPACT to download, read back, and verify design configuration data and create PROM, SVF, STAPL, and System ACE™ CompactFlash solution programming files.

implementation
The mapping, placement and routing of a design. A phase in the design process during which the design is placed and routed.

implementation tools
Tools which implement a design (macros and logic functions) into FPGA CLB and IOB cells.

include files
FPGA and CPLD equation files that are specified by an INCLUDE_EQN statement in a top-level file.

indexes
The left-most and right-most bits of a bus defining the bus range and precision.

InfiniBand
A new industry I/O specification using a 2.5 Gbit/seceond wire speed connection with one, four or twelve wire link widths. Applications include remote storage devices and servers.

INIT pin
A device pin indicating when a device is ready to receive configuration data after power-up.

input
The symbol port through which data is sourced.

input loading
The number of specified unit loads that a specified input represents.

Input/Output Block
A collection or grouping of basic elements that implement the input and output functions of an FPGA.

input pad registers and latches
D-type registers located in the I/O pad sections of the device. Input pad registers can be used instead of macrocell resources.

Install
The Xilinx installation program used to place the Xilinx software on your hard disk or system.instance.

instance
One specific gate or hierarchical element in a design or netlist. The term "symbol" often describes instances in a schematic drawing. Instances are interconnected by pins and nets. Pins are ports through which connections are made from an instance to a net. A design that is flattened to the lowest level constituents is described using primitive instances.

instantiation
The act of placing a symbol that represents a primitive or a macro in a design or netlist.

in-system programming
A methodology in which a complex programmable logic device can be programmed (customized) after it has been soldered or plugged into the user system.

Intellectual Property
A function or algorithm that can be implemented in programmable logic with a defined interface (input, output, and control) and that behaves deterministically based on this interface. IP can be delivered as source code or as an encrypted netlist. In the semiconductor design industry, intellectual property (IP) refers to predefined functions such as processors or bus interfaces that are typically licensed from the software developer. IP can be implemented directly in silicon, either in fixed logic or programmable logic devices, and saves chip designers time during product development. Synonymous with Cores.

interactive
Interactive describes a process or tool that requires interaction with the user in order to execute or accomplish its objective.

interconnect
In programmable logic, silicon devoted to connecting memory elements on the chip to create a logic circuit.

interconnect line
Any portion of a net.

interface program
Any of the Xilinx programs used to translate a design file into a Xilinx format file, an implementation file, or a simulation file.

internal buffer
Memory used by Test Bench Waveform Editor to hold graphics information. This area is separate from the clipboard and copies graphical objects within the Test Bench Waveform Editor.

I/O Port
I/O ports are user I/Os to be assigned to physical package pins. Each I/O signal is defined as a port.

IOB
See Input/Output Block.

IOC
Interrupt On Complete

IOP
I/O Peripherals

IOPB
Instruction-side On-chip Peripheral Bus

IOSTANDARD
A basic mapping constraint and synthesis constraint. Use IOSTANDARD to assign an I/O standard to an I/O primitive. All components with IOSTANDARD must follow the same placement rules (banking rules) as the SelectIO™ technology components.

IOU
Input/Output Unit

IP
See Intellectual Property.

IPG
Inter Packet Gap

IPIC
Intellectual Property Interconnect.

IPIER
Intellectual Property Enable Register

IPIF
Intellectual Property Interface

IPIR
IP Interrupt Register

IPISR
Intellectual Property Status Register

IPR
Interrupt Pending Register

IRQ
Interrupt Request

ISA
Instruction Set Architecture. The ISA describes how aspects of the processor (including the instruction set, registers, interrupts, exceptions, and addresses) are visible to the programmer.

ISC
Interrupt Source Controller

ISE
Integrated Software Environment

ISE Text Editor
Xilinx software that allows you to create, view, and edit text files, such as ASCII, UCF, VHDL, Verilog, and Tcl files.

ISERDES
Input Serializer/Deserializer. See also: SERDES.

ISim
ISE® Simulator software

ISO
International Organization for Standardization

Isochronous data transfer
A time-sensitive data transfer, such as video. It relies on a guaranteed latency and bandwidth.

ISR
Interrupt Status Register

ISS
Instruction Set simulator

iterative design
The process of using a guide file to add changed logic to a design that has already been verified for timing. It implements logic that has not been changed using the same FPGA resources as in the guide file, which ensures that the timing on those paths is identical. For logic that has been changed, it uses the normal mapping, placement, and routing process.

ITM
Instrument trace module (CoreSight sub-module). Applies to Zynq-7000 All Programmable SoC.

IUS
Incisive Unified Simulator

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JEDEC
Joint Electron Devices Engineering Council. A CPLD file format used for downloading device bitmap information to a device programmer.

JESD
JEDEC Standard

JTAG
Joint Test Action Group, IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture

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Karnaugh map
A binary representation of the sums of products of a function. The Karnaugh map is a type of truth table from which simplified equations that define a function are derived. The simplification of such equations is called minimization.

KHz
Kilohertz

KSPS
Kilo-Samples Per Second

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L/T
Length Type

label
Text attached to a bus, pin, net, or component to identify it.

LAN
Local Area Network

latch
A two-state buffer fed by two inputs, D and L. When the L input is Low, the latch acts as a transparent input; in this case, the latch acts as a buffer and outputs the value input by D. When the L input is High, the latch ignores the D input value.

latched input
An input which captures asynchronous inputs.

LBUS
Local Bus

LCA
Logic Cell Array

LCA file
FPGA implementation file.

LCRC
Link CRC

LDMOS
Laterally Diffused Metal Oxide Silicon (Field Effect Transistor)

LDT
See Lightning Data Transport.

Lead/Ball Finish
Material composition of lead plating on lead frame packages and in the solder balls used on BGA packages. Material used for solder bump material in the flip chip package is also reported where applicable.

• Pb = Lead
• Sn = Tin
• Ag = Silver

Level-Sensitive Scan Design
LSSD. A scan-path technique for systems using latches as bistables and two or more independently controllable (two-phase non-overlapping) clocks. System design must also be level-sensitive: the clock rise and fall times should not affect correct operation, and the latches must be hazard-free.

Level-Sensitive Scan Design
LSSD. A scan-path technique for systems using latches as bistables and two or more independently controllable (two-phase non-overlapping) clocks. System design must also be level-sensitive: the clock rise and fall times should not affect correct operation, and the latches must be hazard-free.

LF
Local Fault

LFI
Local Fault Indicator

LFP file
The Logical Floorplan File is created by PACE to store grouping and color settings. You should not edit this file. PACE reads this file automatically if one exists in the same directory as the UCF file.

LFSR
Linear feedback shift register. A shift register with connections from some of the stages to the input of the first element through an exclusive-OR gate (standard form), or a shift register with connections from the last stage to exclusive-OR gates at the inputs of the first and intermediate stages of the register (modular form).

Libgen
Library Generator sub-component of the Xilinx® Platform Studio (XPS) technology.

library
A set of macros, such as adders, buffers, and flip-flops that is part of the Xilinx interface.

LibXil Standard C Libraries
The Xilinx® Embedded Development Kit (EDK) libraries and device drivers provide standard C library functions as well as functions to access peripherals. Libgen automatically configures the EDK libraries for every project based on the Microprocessor Software Specification (MSS) file.

Lightning Data Transport
Lightning Data Transport (LDT) is a chip-to-chip interconnect that provides a bandwidth from 6.4 Gb/sec per eight wire link width, and can support up to 32 links.

.ll file
The logic allocation file, which indicates the bitstream position of storage elements such as latches, flip-flops, and IOB inputs and outputs. The Hardware Debugger uses this file to locate signal values inside a readback bitstream.

LLC
Logical Link Control

LLDP
Link Layer Discovery Protocol

LMB
Local Memory Bus. A low latency synchronous bus primarily used to access on-chip block RAM. The MicroBlaze™ processor contains data and instruction LMBs.

LMFC
Local Multi Frame Clock

LO
Local Oscillator

load
An input port.

loading direction
The direction in which data is stored on your PROM. In the Up direction, the data is stored in ascending order. In the Down direction, the data is stored in descending order.

LOC
See Site Placement Constraint.

locking
A lock constraint in the PCF file locks a component. A lock routing constraint specifies that the current routing cannot be changed or unrouted. A lock placement constraint specifies that placed components cannot be unplaced, moved, or deleted.

LOF
Loss of Frame

logic
One of the three major classes of ICs in most digital electronic systems: microprocessor, memory, and logic. Logic is used for data manipulation and control functions that require higher speed than a microprocessor can provide.

logic allocation file
A file used for probing that has an .ll extension. The file provides bit locations of the values of RAM, I/O, latches, and flip-flops.

logic element
A building block defining the logic in a design. These elements are typically primitives -- that is, flip-flops, AND gates, and such elements -- or macros, higher level combinations of primitives.

logic icon
A graphical representation of a logic resource, such as a flip-flop, buffer, or register.

logic optimization
The process that decreases the area or increases the speed of a design.

logic synthesis
A process that starts from a high level of logic abstraction (typically Verilog or VHDL) and automatically creates a lower level of logic abstraction using a library containing primitives.

logical constraints
Constraints are constraints that are attached to elements in the design prior to mapping or fitting.

long line
A long line connects to a primary global net or to any secondary global net. Long lines carry signals across the length or width of the chip with minimal delay and negligible skew.

look-ahead carry
A technique used to reduce the carry propagation delay in a parallel adder. All carries are added at the same time.

look-up table (LUT)
Look-up tables (LUTs) are used to implement function generators in CLBs. Four independent inputs are provided to each of two function generators (F1-F4 and G1-G4). These function generators can implement any arbitrarily defined Boolean function of four inputs. The H function generator can implement any Boolean function of four inputs. When combined with one or more flip flops, constitutes the basic memory-based programmable logic element in FPGAs.

LOS
Loss of Signal

low
In binary logic, there are two logic levels: High (1) and Low (0). The Low condition represents the low of two voltages, typically 0V.

low skew resources
Secondary routing resources on some devices which provide signal routing with high fanout and low skew. These resources are more flexible then the global routing resources (BUFGs) since they can route any signal, not just clock signals.

LPDDR
Low-power double data rate

LSB
Least Significant Bit / Least Significant Byte

LSSD
See Level-Sensitive Scan Design.

LTE
Long Term Evolution

LTSSM
Link Training and Status State Machine

LUT
See look-up table.

LVDS
Low-Voltage Differential Signaling. A sink node or stopping point for a timing analysis path. The data input of a synchronous element or a pad.

LVTTL
Low Voltage Transistor-Transistor Logic

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MAC
Media Access Controller.

MAC
Multiply and accumulate. A measure of arithmetical performance in digital signal processing systems. FPGAs can achieve some of the highest DSP performance, calculating a half trillion MACs per second.

macro
A component made of nets and primitives, flip-flops, or latches that implements high-level functions, such as adders, subtracters, and dividers. Soft macros and Relationally Placed Macros (RPMs) are types of macros.

macrocell
The CPLD logic cell, which is made of gates only. A macrocell can implement both combinatorial and registered equations.

magnitude comparator
A component whose function is to compare quantities of numbers.

main window
The background against which windows are displayed.

mapping
The process of assigning a design's logic elements to the specific physical elements that actually implement logic functions in a device.

masked programmed gate array
A customizable device that is programmed during the IC manufacturing process.

master-slave flip-flop
Two flip-flops activated in turn and designed to avoid metastability conditions.

Material Data Declaration Sheet
The MDDS template used by Xilinx is based on the Electronic Industries Alliance (EIA) September 19, Material Composition Declaration Guide dated September 19, 2003 for Level A and Level B materials of interest. As per EIA, "Level A” List is composed of materials and substances subject to currently enacted legislation that:

• Prohibits their use and/or marketing
• Restricts their use and/or marketing
• Requires reporting or results in other regulatory effect.

• Precious materials/substances that provide economic value for end-of-life management purposes
• Materials/substances that are of significant environmental, health, or safety interest
• Materials/substances that would trigger hazardous waste management requirements
• Materials/substances that could have a negative impact on end-of-life management

maximal encoding
Maximal encoding is a type of state machine encoding that uses the minimum number of registers to encode the machine. Each register is used to its maximum capability.

MB
Megabyte

Mbps, Mb/s
Megabits per second

MCA
Master Completer Abort

MCH
Multicast Channel

MCS-86
MCS-86 is an Intel PROM format supported by the Xilinx tools. Its maximum address is 1 048 576. This format supports PROM files of up to (8 x 1 048 576) = 8 388 608 bits.

MDC
Management Data Clock

MDD File
Microprocessor Driver Description file

MDDS
See Material Data Declaration Sheet.

MDIO
Management Data Input/Output

MDM
Microprocessor Debug Module

memory unit
A collection of thousands of registers for the storage of digital information.

menu bar
The area located at the top of the main window that provides access to the menus.

MEP
Master Error Poison

metastability
Metastability refers to unknown states occurring when flip-flops change states before the next input. To prevent the problem, use a master-slave flip-flop or implement the flip-flop such that it responds to only one of the clock edges, either negative or positive.

MFS
LibXil Memory File System. The MFS provides user capability to manage program memory in the form of file handles.

MGT
Multi-Gigabit Transceiver

MHS File
Microprocessor Hardware Specification file. The MHS file defines the configuration of the embedded processor system, including buses, peripherals, processors, connectivity, and address space.

MHz
Megahertz

migration

1. The conversion of a design from one device to another. The device may or may not be of the same family.
2. The conversion of design data files from an older version of the Xilinx development system to a more recent version.

MII
Media Independent Interface

MIMO
Multiple Input Multiple Output

minimization
The process of reducing a logic function to a sum-of-products expression consisting of the least number of product terms.

MIO
Multiuse I/O

MISO
Master In Slave Out

mixed mode design
A design that consists of both schematic and behavioral blocks.

MLD
Microprocessor Library Definition file

MM2S
Memory Map to Stream

MMCM
Mixed-Mode Clock Manager

MMD
MDIO Managed Device

MMU
Memory Management Unit

model registry
A list (which may include schematics, Electronic Design Data Model (EDDM) single objects, and symbols) that identifies what models can be used to describe a component.

MODF
Mode-Fault error

module

1. Any block or symbol.
2. A bound design element where the bounds are defined with inputs and outputs. The module represents a logical function with outputs based on the value of the inputs.
3. A Module block or primitive that is a basic library element or building block. All designs must eventually be broken down to the primitive level by the implementation tools in order to represent the implemented hardware design.

MOSI
Master Out Slave In

MP
Memory Polynomial

MPD File
Microprocessor Peripheral Definition file. The MPD file contains all the available ports and hardware parameters for a peripheral.

MPLB
Master Processor Local Bus

MPMC
Multi-Port Memory Controller

MPS
Maximum Payload Size

MPU
Microprocessor Unit

MRL
Memory Read Line

MSDPD
Mixed Signal Digital Pre-Distortion

MSE
Master SLVERR. See also: SLVERR.

MSI
Messaged Signaled Interrupt

MSK
Minimum Shift Keying

MSPS
Mega-Samples Per Second

MSR
Mode Select Register

MSS File
Microprocessor Software Specification file

MTU
Maximum Transmission Unit

multicycle path
A path between two registers with a timing requirement that is a multiple of the clock period for the registers.

multiplexer
A reprogrammable routing control. This component selects one input wire as output from a selection of wires.

MUR
Master Unsupported Request. See also: UR.

MWI
Memory Write Invalidate

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NAK
Not Acknowledged

NCD
Native Circuit Description

NCF File
Netlist Constraints File

NCO
Numerically Controlled Oscillator

ND
New Data

NDA
Non Disclosure Agreement

net

1. A logical connection between two or more symbol instance pins. After routing, the abstract concept of a net is transformed to a physical connection called a wire.
2. An electrical connection between components or nets. It can also be a connection from a single component. It is the same as a wire or a signal.

net name
A name that identifies a net.

netlist
A text description of the circuit connectivity. It is basically a list of connectors, a list of instances, and, for each instance, a list of the signals connected to the instance terminals. In addition, the netlist contains attribute information.

network
A collection of logic elements and the wires (nets or connections) that define how they interconnect.

NGC File
The Native Generic Curcuit (NGC) file is a netlist file that contains both logical design data and constraints. This file replaces both Electronic Data Interchange Format (EDIF) and Netlist Constraints File (NCF) files.

NGD
A Native Generic Database file that describes the logical design reduced to Xilinx primitives.

NGD2EDIF
A program that translates a design into an EDIF 2 0 0 netlist in terms of the Xilinx primitive set. It allows you to simulate pre-route and post-route designs.

NGDBuild
A Xilinx program that performs all the steps necessary to convert all EDIF or NGC format design netlists and then writes the results into a single merged NGD file describing the logical design.

NGM
A design file produced by MAP that contains information about the logical design and information about how the logical design corresponds to the physical design.

NGO File
A Xilinx specific format binary file containing a logical description of the design in terms of its original components and hierarchy.

node
The junction of nets joined throughout the design hierarchy by pins on symbols.

NPI
Native Port Interface

NRE
Non-recurring Engineering. In the world of fixed logic chip design, refers to the one-time, up front costs customers incur in designing a chip. Includes software tools, engineering time, design verification, mask sets and prototypes. In the programmable logic world, usually refers to the expenses associated with converting a PLD design to a fixed logic design to gain a cost reduction.

number of clock cycles
The number of clocks that have been applied between snapshots during synchronous mode debugging. This value is displayed between the snapshot numbers on the horizontal axis.

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OBSAI
Open Base Station Architecture Initiative

OCM
On-Chip Memory

ODELAY
Output logic delay

offset
Defines the timing relationship between an external clock and its associated data-in or data-out pin.

one-hot encoding
A type of encoding in which an individual state register is dedicated to only one state. Only one flip-flop can be active, or hot, at a time. The bit position represents the value. For example, in state machine language, each state is assigned its own storage register (flip-flop) and only one state can be active at a time.

one-to-one logic
In Xilinx® FPGAs, one-to-one logic is the exact correspondence between the logic specified in the design entry phase and the logic implemented in the device. For example, if you draw three inverters in your design, there are three corresponding inverters in the programmed device. This correspondence makes back-annotation of timing delays very straightforward and ensures that there are no differences between your original design and the finished device.

ONFI
Open NAND Flash Interface

OOR
Out of Range

OPB
On-chip Peripheral Bus

open box methodology
Open box methodology uses Xilinx® Design System (XDS) interactively for the implementation process. It is traditionally referred to as the "manual flow."

optimization
The process that decreases the area or increases the speed of a design.

optimizer
A program which performs logic optimization.

options
Features that modify the way a program runs. Options are generally set by the user.

oscillator
A bi-stable circuit that can be used as a clock. The stable states are 0 and 1.

OSD
On Screen Display

OSERDES
Output Serializer/Deserializer. See also: SERDES.

OSI
Open Systems Interconnection

OT
Over Temperature

OTG
(USB) On-the-Go

output delay
The maximum time allowed for an output to settle and be properly recognized by other logic inputs.

overflow
An indication that a value cannot be represented in a given number of bits. It is a signal that can be translated as an error or ignored. In a design, this error can be interpreted as a signal. Also defined as a condition that occurs when incoming data exceeds the storage capacity of the input buffer.

OVI
Open Verilog International. A non-profit organization that exists to promote, maintain, and support the use of Verilog HDL worldwide. OVI supports the IEEE 1364 standard for Verilog HDL.

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P1dB
One-decibel compression point

PA
Power Amplifier

PACE
Pinout Area Constraints Editor. A GUI tool that defines legal pin assignments and creates properly sized area constraints.

package
The physical packaging of a chip, for example, PG84, VQ100, and PC48.

Package Designator
Materials listed are package related. To relate information to a specific device part number, refer to the package designator portion of the part number. For example: XC3S200-4TQ144C. The bold, underlined section represents the package designator. For Pb-free packages, an additional "G" is added to the package designator. For example: TQ144 (standard) would be TQG144 (Pb-free).

Package Pin
Package pins are the physical pins of the package to which I/O ports are assigned. The package pins are grouped into I/O banks. Refer to the device specifications for more information about the package pins and I/O banks.

Packet
A unit of data transferred across a PCI EXPRESS® link. The three types of packets are TLPs, DLLPs, and PLPs.

pad
The physical bonding pad on an integrated circuit. All signals on a chip must enter and leave by way of a pad. Pads are connected to package pins in order for signals to enter or leave an integrated circuit package.

pad-to-pad path (P2P)
A path which starts at an input of the chip and ends at an output of the chip. The pad-to-pad path time is the maximum time required for the data to enter the chip, travel through logic and routing, and leave the chip. It is not controlled or affected by any clock signal.

pad-to-setup path (P2S)
A path which starts at an input of the chip and ends at an input to a flip-flop, latch, or RAM--wherever there is a setup time against a control signal. The pad-to-setup path time is the maximum time required for the data to enter the chip, travel through logic and routing, and arrive at the output before the clock or control signal arrives.

PAL
See Programmable Array Logic.

PAO File
Peripheral Analyze Order file. The PAO file defines the ordered list of Hardware Description Language (HDL) files needed for synthesis and simulation.

PAR

1. Peak-to-Average Ratio.
2. See Place and Route.

parallel adder
An adder implementation in which the bits are added simultaneously. The carries of the parallel adders are connected, thus generating the sum simultaneously.

Parallel Cable III
A cable assembly which contains a buffer to protect the parallel port of your PC and a set of headers to connect to your target system.

PARTGen
A command which displays various levels of information about installed Xilinx devices and families depending on which options are selected.

partitioning

1. The process of splitting a single design among multiple devices.
2. The maximum level of integration (density concern).

path
A connected series of nets and logic elements. A path has a start point and an end point that are different depending on the type of path.

path delay
The time it takes for a signal to propagate through a path.

PBCH
Physical Broadcast Channel

PBD File
Processor Block Diagram file

PCB
Printed Circuit Board

PCC
Predictive Command Controller

PCF files
Physical Constraints File. This file contains the physical constraints that are derived from the logical constraints after mapping. Any changes in constraints in the FPGA Editor are also written to the PCF.

PCFICH
Physical Control Format Indicator Channel

PCH
Paging Channel

PCI
Peripheral Component Interconnect

PCIBAR
Peripheral Component Interconnect Base Address Register

PCS
Physical Coding Sublayer

PDA
Parallel Distributed Arithmetic

PDCCH
Physical Downlink Control Channel

PDF
Portable Document Format

PDSCH
Physical Downlink Shared Channel

period
A clock period specification checks timing between all synchronous elements within the clock domain as defined in the destination element group. The group may contain paths that pass between clock domains if the clocks are defined as a function of one or the other. The period specification is attached to the clock net.

PERR
Parity Error

PHICH
Physical HARQ Indicator Channel

PHY
Physical-side interface

PHYAD
Physical Address

Physical Block (Pblock)
A Pblock is defined in the PlanAhead™ software during floorplanning. Traditionally, a single or group of logic instances are assigned to a Pblock. The Pblock can have an area, such as a rectangle defined on the FPGA device, to constrain the logic. Netlist logic placed inside of Pblocks will receive AREA_GROUP constraints for the ISE® software. Pblocks may be specified with specific RANGE types to contain various types of logic only (such as SLICE, RAM/MULT, and DSP). Pblocks can be defined with multiple rectangles to enable non-rectangular shapes to be created, such as ‘L’ shaped and ‘T’ shaped.

physical constraints
Constraints that are attached to design elements in the physical design, that is, the design after mapping has been performed. These constraints are defined in the Physical Constraints File (PCF), which is created during mapping.

Physical Layer
The lowest of the three layers in the PCI EXPRESS® architecture.

PID
packet identifier field of USB packet

PIM
Physically Implemented Module. A term used in modular design that refers to the individual modules that have been completed and are ready to be incorporated into the top-level design.

pin
A symbol pin or a package pin. A package pin is a physical connector on an integrated circuit package that carries signals into and out of an integrated circuit. A symbol pin, also referred to as an instance pin, is the connection point of an instance to a net.

pin feedback
Pin feedback specifies that the associated signal comes from the actual device pin and not from the universal interconnect matrix (UIM).

PIN2UCF
A Xilinx program that generates pin-locking constraints in a UCF file by reading a placed NCD file for FPGAs or GYD file for CPLDs. PIN2UCF writes its output to an existing UCF file. If there is no existing UCF file, PIN2UCF creates a new file.

PIP
See Programmable Interconnect Points.

PL
Programmable Logic in the Zynq-7000 All Programmable SoC. Equivalent to the FPGA in the 7 series devices

PLA
Programmable Logic Array

Place and Route
Place and Route (PAR) is a program for placing and routing an FPGA design. The process is called design implementation. Using back-end implementation software tools, Place and Route is the process of connecting various memory elements in an FPGA to create a custom logic circuit.

placer
A utility that maps logic from your design into specific locations in the target FPGA.

placer effort
The user-controlled parameter that balances run-time with placement efficiency.

placing
The process of assigning physical device cell locations to the logic in a design.

Platform
Xilinx defines platform as an umbrella term encompassing a set of technologies compiled and presented to customers as part of the design ecosystem. See also: Targeted Design Platform.

Platgen
Hardware Platform Generator sub-component of the Xilinx® Platform Studio (XPS) technology.

PLB
Processor Local Bus

PLD
Programmable Logic Device. An integrated circuit composed of two types of gate arrays: the AND array and the OR array, thus providing for the sum of products algorithmic representations. PLDs include three distinct types of chips: PROMs, PALs, and PLAs. The most flexible device is the PLA in which both the AND and OR gate arrays are programmable. In the PROM device, only the OR gate array is programmable. In the PAL device, only the AND gate array is programmable. PLDs are programmed by blowing the fuses along the paths that must be disconnected. FPGAs and CPLDs are classes of PLDs.

PLL
Phase-Locked Loop

PLP
Packet Layer Protocol

PLUSASM
A Xilinx proprietary Boolean equation language for expressing behavioral designs mapped to Xilinx® CPLDs.

PMA
Physical Medium Attachment

PMCH
Physical Multicast Channel

PMD
Physical Medium Dependent

port
A logical connector that associates signals across hierarchical boundaries. Port location refers to a package pin on the IC.

POS-PHY4
Also, PL4. A 13.3 Gbit/second parallel link layer to physical layer interface for packet and cell transfer over SONET for OC-192c and 10 G bit/second Ethernet applications. POS-PHY4 is a 16-bit point-to-point interconnect with 832 Mb/sec per bit signaling utilizing double data rate clocking.

post-synthesis simulation
Simulation which is usually done after the HDL code has been expanded into gates. Post-synthesis simulation is similar to behavioral simulation since design behavior is being checked. The difference is that in post-synthesis simulation the synthesis tool's results are being checked. If post-synthesis and behavioral simulation match, the HDL synthesis tool has interpreted the HDL code correctly.

PRBS
Pseudo-Random Binary Sequence

PRCR
PCIe® Requester Control Register

PRIDR
PCIe® Requester ID Register

primitives
The simplest design elements in the Xilinx libraries. Primitives are the design element "atoms," and can be combined to create macros. Examples of Xilinx primitives are the simple buffer, BUF, and the D flip-flop with clock enable and clear, FDCE.

probing
The process of examining the states of a device.

process
A running concurrent block of logic.

process technology
The procedure used to convert blank silicon wafers into finished wafers containing hundreds to thousands of chips. These chips are tested and assembled into plastic or ceramic packages before final use.

Product Mass
The product mass represents an average weight in grams. Package weights will vary slightly based on the die used in the package.

product of sums
The complement expression of a sum of products. Specifically, the outputs of a function for which the input combinations equal 0.

Product Term
The basic memory-based programmable logic element in CPLDs.

product term cascading
The process of passing groups of four product terms from one macrocell to another for the purpose of increasing the number of usable product terms.

Programmable Array Logic
A programmable logic device that consists of a programmable AND matrix whose outputs drive fixed OR gates. This was one of the earliest and, in terms of logic density, the simplest forms of programmable logic. PALs can implement small functions easily (up to a hundred gates) and run very fast, but they are inefficient for large functions.

Programmable Interconnect Points
The circuits that provide the routing paths used to connect the inputs and outputs of IOBs and CLBs into logic networks. A PIP is made of a CMOS transistor, which you can turn on and off to activate the PIP.

programmer
A hardware box and its associated software that is used to program either the FPGA/CPLD devices themselves or the memory devices that are used to store programming data.

programming
The process of configuring the programmable interconnect in the FPGA.

Project Navigator
The main window for ISE®. All of the GUI design tools for the ISE Design Suite are accessed through the Project Navigator software.

PROM
A programmable read-only memory.

PROM file
One or more BIT files (bitstreams) formed into one or more datastreams. The file is formatted in one of three industry-standard formats: Intel MCS86 HEX, Tektronics TEKHEX, or Motorola EXORmacs. The PROM file includes headers that specify the length of the bitstreams as well as all the framing and control information necessary to configure the FPGAs. It can be used to program one or more devices.

PROMGen
A Xilinx program that formats a BitGen-generated configuration bitstream (BIT) file into a PROM format file. The PROM file contains configuration data for the FPGA.

propagation
The transmission of signal from one point in a design to other points. Constraint propagation refers to all of the design elements and nets that apply to a specified constraint in a design.

prototyping

1. The first full-scale functional model of a new device.
2. The use of a model prior to the generation of a final version of a chip.

PS
Processing System. The new processor portion of the Zynq-7000 All Programmable SoC.

PSC
Parallel-to-Serial Shift Register

pseudo logic
Logic that is temporarily inserted in a design to facilitate the relative placement of the connected logic within a module. Pseudo logic is used when performing modular design.

PSF
Platform Specification Format. The specification for the set of data files that drive the Xilinx® Embedded Development Kit (EDK) tools.

PSK
Phase Shift Keying

PSR
PCIe® Status Register

PTM
Program Trace Macrocell (debug/trace sub-module)

PTP
Precise Timing Protocol

pull-down resistor
A device or circuit used to reduce the output impedance of a device, often a resistor network that holds a device or circuit output at or less than the zero input level of a subsequent digital device in a system.

pull-up resistor
A device or method used to keep the output voltage of a device at a high level, often a resistor network connected to a positive supply voltage.

PWM
Pulse Width Modulation

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Q
Quadrature

QAM
Quadrature Amplitude Modulation

QM
Quadrature Modulator

QMC
Quadrature Modulator Correction

QW, QWORD
Quad Word. Eight bytes.

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R/W
Read/Write

R/WC
Read/Write to Clear

RAC
Read Address Channel Controller

race check
An analysis that compares the time it takes for data to propagate from a source register to a destination register with the amount of skew on the clock lines driving each register. A race condition exists if the clock skew is greater than the propagation time plus the hold time.

radix
The base--usually binary, octal, decimal, or hexadecimal-- in which waveforms are displayed in a waveform viewer.

RAM
Random Access Memory. A read and write memory that has an access time independent of the physical location of the data.

RAM-based FPGA
An FPGA whose configuration data is programmed into random access memory. These devices are re-programmable.

RapidIO
A next-generation switched-fabric interconnect architecture for embedded systems that is optimized for both high bandwidth and low latency. Initial implementations are expected to exceed 1.0 Gbit/second throughput based on clock rates from 250 MHz and higher. Applications will include embedded systems in the networking, multimedia, storage and signal-processing sectors.

rat's nest
A diagram consisting of lines that indicate connectivity between logic placed in the Floorplanner window.

RBT file
A raw BIT format file. The ASCII version of the BIT file.

RC
Root Complex

RCB
Read Completion Boundary

RC/EP
Root Complex/Error Poison

RDC
Read Data Channel Controller

RE
Radio Equipment

readback
The process of reading the logic downloaded to an FPGA back to the source. There are two types of readback:

1. A readback of logic usually accompanied by a comparison check to verify that the design was downloaded in its entirety.
2. A readback of the states stored in the device memory elements to ensure that the device is behaving as expected.

Reconfigurable Computing
A methodology of using programmable logic devices in a system design such that the hardware-based logic can be changed to perform various tasks. Benefits includes the use of fewer components, less power, and the flexibility that bring about. Also allows networked equipment in the field to be upgraded or repaired remotely.

REGAD
Register Address

registers
Digital circuits that store bits (1s and 0s).

Relationally Placed Macros
Any "soft macro" that contains one or more RLOC constraints to specify relative placement. It can be as simple as "make sure these two flip-flops get placed in the same slice", to a full-blown specification of the relative placement every LUT, MUX, and flip-flop.

Relative Mins
Relative Minimum Delays. The minimum delay value(s) when operating at specified operation conditions (temperature and voltage).

resistance

1. The property -- based on material, dimensions, and temperature of conductors -- that determines the amount of current produced at a given difference in potential. A material's current impedance that dissipates power in the form of heat.
2. The drive of the output pins on a network.

resource graphics
Graphical representations of elements in the target FPGA Floorplan window, such as function generators, registers, and 3-state buffers in the CLB and IOBs.

RF
Read FIFO Register

RFI
Register File Interface

RFI
Remote Fault Indicator

RFO
Read FIFO Occupancy Register

RGB
Red Green Blue

RGMII
Reduced Gigabit Media Independent Interface

ripple counter
A series connection of complementing flip-flops. Ripple counters are also called asynchronous counters.

RMS
Root Mean Square

RO
Read Only

RoHS Compatible
Xilinx defines RoHS to mean products that are compatible with the current RoHS requirements for all six substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, Xilinx Pb-free / RoHS products are suitable for use in specified Pb-free processes.

ROM
Read Only Memory. A static memory structure that retains a state indefinitely, even when the power is turned off. It can be part of a function generator.

router
The utility that connects all appropriate pins to create the design's nets.

router effort
Router effort refers to the user-controlled parameter that balances run-time with routing efficiency.

routing
Routing is the process of assigning logical nets to physical wire segments in the FPGA that interconnect logic cells.

routing layer
A routing layer is a conductive layer used for interconnections.

RPM
A Relationally Placed Macro (RPM) defines the spatial relationship of the primitives that constitute its logic. An indivisible block of logic elements that are placed as a unit into a design.

RRU
Remote RF Unit

RS
Reconciliation Sublayer

RTC
Real Time Clock

RTL

1. Resistor Transistor Logic.
2. Registor Transfer Level.

RTL Viewer
Xilinx software that allows you to view a schematic representation of the pre-optimized design in terms of generic symbols that are independent of the targeted Xilinx device, for example, in terms of adders, multipliers, counters, AND gates, and OR gates.

RTR
Remote Transmission Request

RTT
Round Trip Time

Run
A synthesis or implementation attempt. Each Run is associated with a specific strategy. You can launch multiple runs either simultaneously with multiple processors or serially. Runs will be queued sequentially with the status displayed in the PlanAhead™ software.

RW
Read/Write

RWC
Read/Write to Clear

RX, rx
Receiver

RXAUI
Reduced Pin eXtended Attachment Unit Interface

RXEOF
Receive End of Frame

RXSOF
Receive Start of Frame

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S2MM
Stream to Memory Map

SA
Source Address

SBO
Slave BAR Overrun

SCA
Slave Completer Abort

Scalable Optimized Architecture
Describes the fact that all 7 series FPGA device families, from low end to ultra high end, are built with the same core building blocks of logic, memory, DSP, clocking, etc.

scan test
A synchronized procedure for testing CLB and IOB blocks.

Schematic and Symbol Editors
Xilinx software that allows you to create, view, and edit schematics and symbols for schematic design entry.

SCK
Serial Clock

script
A series of commands that automatically execute a complex operation such as the steps in a design flow.

SCT
Slave Completion Timeout

SCU
Snoop Control Unit in a Zynq-7000 All Programmable SoC.

SD/SDIO
SD/SDIO memory device host controller

SDA
Serial Distributed Arithmetic

SDF
See Standard Delay Format.

SDI
SAP Defect Indicator

SDK
Software Development Kit

SDMA
Soft Direct Memory Access

SDR
Single Data Rate

SD/SDIO
SD/SDIO memory device host controller

seed
A random number that determines the order of the cells in the design to be placed.

seed-place
The act of initial placement with a seed.

SelectMAP Mode
A configuration mode that provides 8-, 16-, 32-bit bidirectional data bus interface to configuration logic that can be used for configuration and readback.

SelectRAM
Refers to the on-chip RAM (built from look-up tables) that can be dual-port or single-port. SelectRAM™ memory applies to both distributed, LUT-based RAM and block RAM.

SEP
Slave Error Poison

SERDES
Serializer/Deserializer. See also: OSERDES.

SERR
System Error

set/reset
This operation is made possible by the asynchronous set/reset property. This function is also implemented by the Global Reset STARTUP primitive.

setup time
The amount of time required for a data input to be stable prior to the triggering edge of a clock device.

SEU
Single Event Upset

SF
Store and Forward

SFD
Start of Frame Delimiter

SFP
Small Form-factor Pluggable

SG
Scatter Gather

SGMII
Serial Gigabit Media Independent Interface

shift register
A register in which data is loaded in parallel and shifted out of the register again. It refers to a chain of flip-flops connected in cascade.

SIB
Slave Illegal Burst

SIE
Serial Interface Engine

signal
A wire or a net.

signal aliasing
The name of a net used to refer to all equivalent nets in a design. Signal aliasing is the process of assigning the name of a bus to a lesser bus or signal contained in the larger bus.

signal binding
The process of joining nets from a lower-level XNF file to pins in a top-level XNF file.

Simgen
Simulation Generator sub-component of the Xilinx® Platform Studio (XPS) technology.

simulation
The process of verifying the logic and timing of a design.

simulation network
A file submitted to the simulator for functional or timing simulation.

Simultaneously Switching Outputs
SSOs. The occurrence of voltage spikes on the ground or power levels inside a chip primarily due to current changes in the combined inductance of ground pins, bond wires, and ground metalization. This problem frequently occurs when multiple outputs change state simultaneously.

single-length line
A line which is switched at every switch matrix it crosses.

Site
The PlanAhead™ software displays a tile grid representation of the specific FPGA resources that can be used to implement the design netlist. Primitive logic sites are displayed and are available for placement of netlist instances. These sites vary in shape and color to differentiate the object types (for example, RAMs, MULTs, CLBs, DSPs, PPCs, and serial transceivers). Leaf-level logic can be assigned to specific slices with placement constraints “LOCs”, or to gates within the slice with LOC and BEL constraints.

Site Placement Constraint (LOC)
Location constraints or LOCs can be assigned to the leaf-level instances that have fixed placement sites assigned to a specific SLICE coordinate. These are different than BEL constraints as they do not lock the logic into specific logic gates within the SLICE. Assigning a LOC constraint will result in a LOC constraint being “fixed” and applied in the exported UCF files for the instance. Depending on zoom level, these LOCs appear in the Device view either as rectangles within their respective assigned sites or logic functions symbols within the site.

SJW
Synchronization Jump Width

skew
Clock to signal delay.

slack
The difference between the constraint and the analyzed value, with negative slack indicating an error condition.

slew
Transition time of an output signal. A fast slew rate has a quicker transition time and a slow rate a longer one. Limiting the slew rate reduces output switching surges in a device. Slew rate can be set to FAST or SLOW.

slew rate
The speed with which the output voltage level transitions from high to low or vice-versa. The slew rate determines how fast the transistors on the outputs change states.

slice
A slice is a fundamental building block of the FPGA, containing LUTs and registers. There are two slices in each Configurable Logic Block (CLB), though the specific contents of the slice may vary with the device family. There are three types of slices: SLICEM, SLICEL, and SLICEX.

SLL
Super Long Line

SLR
Super Logic Region

SLVERR
Slave Error status in AXI4. See also: MSE.

SMC
Static Memory Controller

SMP
Symmetrical multiprocessing. Typically, the CPUs run the same operating system image and use the same resources. Applies to Zynq-7000 All Programmable SoC.

SoC
System-on-Chip. A chip that holds the necessary hardware and electronic circuitry (programmable logic, memory, processing, peripheral interfaces, clocking, and IO) for a complete system.

SOF
Start Of Frame

soft macros
Library design element "macros" that are built hierachically from simpler library elements (for example, a counter built from flip-flops and gates). These are "soft" in the sense the tools are free to remap, place and route them as they see fit. Designers can also build "soft" macros, with or without RLOC constraints to specify relative placement. The tools are free to manipulate the mapping, placement and routing, within the boundaries of the specified constraints. It is possible to so completely constrain a "soft" macro with RLOCs, that every placement is specified and there is nothing left for the tools to decide. Because it still has a logical representation in the design capture, it is still considered "soft".

SOP
Start of Packet

source
An output pin that drives a path. Sources are input pads and the outputs of synchronous elements. Projects can be created with a variety of input file formats. Projects can be created by importing RTL source files in Verilog and VHDL, IP core modules and synthesized netlists in NGC or EDIF format. These files are considered source files.

speed
Speed is a function of net types, CLB density, switching matrices, and architecture.

speed file
A Xilinx® Design System (XDS) data file that contains information defining the timing for each speed grade available for a device.

SPEEDPRINT
A command which lists block delays for a device's speed grade. This program supplements data sheets, but does not replace them.

SPI
Serial Peripheral Interface

SPICR
Serial Peripheral Interface Control Register

SPIDRR
Serial Peripheral Interface Data Receive Register

SPIDTR
Serial Peripheral Interface Data Transmit Register

SPIE
Serial Peripheral Interface Interrupt Enable

SPISEL
Serial Peripheral Interface Slave Select Line

SPISR
Serial Peripheral Interface Status Register

SPISSR
Serial Peripheral Interface Slave Select Register

SPLB
Slave Processor Local Bus

SR
Status Register

SRAM
Static Random Access Memory or volatile memory. SRAM holds a value as long as power is continually supplied. It loses its contents when the power is turned off.

SRP
Stream Reservation Protocol

SRR
Software Reset Register

SRST
Software Reset

SSI
Stacked Silicon Interconnect

SSOs
See Simultaneously Switching Outputs.

STA

1. Static Timing Analysis.
2. Station Management Entity.

Standalone Library
A set of software modules that provide processor-specific access functions. The Standalone library is designed for use when an application accesses board or processor features directly (without an intervening OS layer).

Standard Delay Format
An industry-standard file format for specifying timing information. It is usually used for simulation.

standard encoding
A type of state machine encoding that forms clusters of states and uses binary encoding for each cluster. One-hot encoding is a special case of standard encoding in which each cluster contains exactly one state. Binary encoding is a special case in which all states belong to a single cluster.

STARTUP symbol
A symbol used to set/reset all CLB and IOB flip-flops.

static timing analysis
A point-to-point delay analysis of a design network with respect to a given set of constraints. It does not include insertion of stimulus vectors. This method used by the Interactive Timing Analyzer tool produces detailed timing constraint, clock, and path analysis for post-map or post-place-and-route implementations

static timing analyzer
A tool that analyzes the timing of the design on the basis of its paths.

status bar
An area located at the bottom of a tool window that provides information about the commands that you are about to select or that are being processed.

step
The length of time that each value in a clock pattern is simulated.

step size
The length in nanoseconds of one step of a clock pattern.

Sticky register
A register that retains its state through a hot reset.

stimulus information
The information defined at the schematic level and representing a list of nodes and vectors to be simulated in functional and timing simulation.

STL
Standard Template Library

Strategy
A Strategy is a predefined set of tool command-line options. You can apply factory delivered Strategies or create your own. Strategies can be applied to individual runs.

STS
Status Stream

submicron technology process
A generic name for modern IC manufacturing methods where dimensions on the wafer can be controlled to tolerances well below one micron, which is one millionth of a meter.

SUC
Slave Unexpected Completion

sum of products
The outputs of a function for which the input combinations equal 1.

SUR
Slave Unsupported Request

SVF
Serial Vector Format

SWDT
System Watchdog Timer

switch matrix
A collection of transistors located between CLBs that enables the connection of two interconnect lines. PAR uses the switch matrices and interconnects to connect CLB inputs and outputs. Switch matrices reduce some of the net delay. They have three possible directions: top, bottom, and left.

symbol
A graphical representation of one level of hierarchy.

symbolic state machine
A state machine that makes no reference to the actual values stored in the state register for the different states in the state table. The software determines what these values should be. All that is defined in a symbolic state machine is the relationship among the states in terms of how input signals affect transitions between them, the values of the outputs during each state, and in some cases, the initial state.

synchronous clock
Synchronous control in which flip-flops are set or reset on the rising edge of the clock.

synchronous debug
A debug mode in which you use a cable to have full control of the clock.

synthesis
A process that starts from a high level of logic abstraction (typically Verilog or VHDL) and automatically creates a lower level of logic abstraction using a library containing primitives.

synthesis package
A fixed library of cells, each cell containing the implementation details in terms of primitive logic.

SYSMON
System Monitor

SYSMONRR
XADC Reset Register

SZ
Size Register

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T_DCI
3-state Digitally Controlled Impedance

TAP
Test Access Port

Targeted Design Platform
A Xilinx-specific term that describes the integration of five key components into a common development and run-time environment for FPGA designs, including:

• Design tools supporting different design methodologies
• Boards
• Intellectual property cores
• FPGA silicon devices
• Targeted reference designs

TBI
Ten-Bit Interface

TBR
Timebase Register

Tcl
An acronym for Tool Command Language, which is a scripting language used for rapid prototyping, scripted applications, graphical user interfaces, and testing. Tcl was created by John Ousterhout. A Tcl file has a .tcl extension.

TCP/IP
Transmission Control Protocol/Internet Protocol

TCSR
Timer Control Status Register

TD
Transfer Descriptor

TDD
Time Division Duplex

TDM
Time Domain Multiplexed

TD-SCDMA
Time Division Synchronous Code Division Multiple Access

Technology Viewer
Xilinx software that allows you to view a schematic representation of the design in terms of logic element optimized to the target Xilinx device or "technology," for example, in terms of LUTs, carry logic, I/O buffers, and other technology-specific components. The Technology Viewer also includes Technology View-Exploration Mode, which allows you to view a schematic representation of timing paths in the design to assist with design and timing analysis.

TEKHEX
A Tektronix PROM format supported by Xilinx. Its maximum address is 65 535. This format supports PROM files of up to (8 x 65 536) = 524 288 bits.

TEMAC
Tri-Mode Ethernet MAC

testbench
An HDL netlist containing test vectors to drive a simulation.

threshold
The crossover point when something occurs or is observed or indicated. The CMOS threshold and TTL threshold are examples.

TIG
Timing Ignore

time group
A collection of design elements, including nets, BELs, components, and so forth that can be used to constrain many objects in the same way.

time process
A process which takes the routed nets in the design and calculates the delays associated with each.

timespecs
Commands (which can be specified in a HDL flow or in an external file) that specify the timing requirements of a design to the place and route software.

timing
The process that calculates the delays associated with each of the routed nets in the design.

timing constraints
A series of constraints applied to a given set of paths or nets that dictates the desired performance of a design. Constraints may be period, frequency, net skew, maximum delay between endpoints, or maximum net delay.

timing simulation
Simulation that takes place after the HDL design has been synthesized and placed and routed. The purpose of this simulation is to check the dynamic timing behavior of the HDL design in the target technology. Use the block and routing delay information from the routed design to assess the circuit behavior under worst-case conditions.

timing specifications
Specifications which define the maximum allowable delay on any given set of paths in a design. Timing specifications are entered on the schematic.

Tin (Sn) Whisker Mitigation
Xilinx believes the risk of Sn whisker is very low if the process is well controlled. Xilinx recommends annealing products that use Matte Sn plating on the leads for 1 hr @ 150 C. Xilinx has seen data that shows that anneal is an effective whisker mitigation method. Research shows that whisker is a result of stress build up in the plating. Anneal alleviates the stress in the plating by producing a uniform inter-metallic layer.

TL
See Transaction Layer.

TLIF
Transaction Layer Interface

TLP
Transaction Layer Packet

TLR1
Timer1 load register

TLR0
Timer0 load register

TMR
Test Mode Register

TNM
The Timing attribute part of TIMESPEC and specification.

TOE
TCP/IP Offload Engine

top-down design
An HDL methodology where overall design behavior is defined first and then HDL blocks. It is a process that starts a design with the highest level of abstraction and gradually designs underlying blocks until the complete design is implemented in the target technology. Top-down design is often technology-independent at the highest levels of design abstraction.

top-level file
The main file of a PLUSASM design. It contains design control information. It also contains either design equations or references to include files containing design equations.

TOW
Toggle-On-Write

TRACE
The Timing Reporter And Circuit Evaluator. A Xilinx command line utility for performing static timing analysis of a design based on input timing constraints. Its two major functions are timing verification and reporting.

trace information
A list of nodes and vectors to be simulated in functional and timing simulation. This information is defined at the schematic level.

Transaction Layer
The uppermost of the three layers of the PCI EXPRESS® architecture.

translation tools
Programs that create Xilinx format files. For example, EDIF2NGD translates CAE designs into NGD format files.

trimming
The process of removing unconnected or unused logic.

3-state buffer
A buffer that places an output signal in a high-impedance state to prevent it from contending with another output signal.

tristate condition
A high-impedance state. A tristate can act also as a normal output; i.e. it can be on, off, or not connected.

TSB
Time-Skew Buffer

TTC
Triple Time Counter

TTY
A textual command line interface.

TWR
Timing Wizard Report

TX, tx
Transmitter

TX HPB
Transfer High Priority Buffer

TXEOF
Transmit End of Frame

TXSOF
Transmit Start of Frame

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UAF
Use Acceptance Filter

UAR
USB Address Register

UART
Universal Asynchronous Receiver-Transmitter

UCF
See User Constraints File.

UDT
Up/Down Count Timer

UI
Units of Issue

UIM
Universal Interconnect Matrix. The routing matrix for CPLD devices. This fully populated switching matrix allows any output to be routed to any input, guaranteeing 100% routability of all designs. The UIM can also function as a very wide AND gate, which can allow more logic to be placed in macrocells.

UIM_AND function
An AND gate created from the inherent wired-AND structure of the UIM. It requires no macrocell resources.

UIM feedback
UIM feedback specifies that the associated signal comes from the macrocell and not from the device pin.

ULPI
Universal Low Pin Interface

UMTS
Universal Mobile Telecommunications System

unbonded
An IOB used for internal logic only. This element does not have an external package pin.

underflow
A condition that occurs when an attempt is made to read data from an empty buffer.

Unified Libraries
A set of logic macros and functions that are used to define the logic of a design. The elements are compatible across families and schematic and HDL editors.

unit load
A measure of impedance presented to an input or output under specified conditions.

UPAR
ULPI PHY Access Register

UR
Unsupported Request. See also: MUR.

USB Cable
Universal Serial Bus cable. USB I/USB II. Programming cables used by iMPACT when programming and reading back configuration files.

User Constraints File
The user constraints file (UCF) is an ASCII file specifying constraints on the logical design. These constraints affect how the logical design is implemented in the target device. You can use the file to override constraints specified during design entry.

UTMI
Universal Transceiver Macrocell Interface

UTRA-FDD
UMTS Terrestrial Radio Access - Frequency Division Duplexing

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VCO
Voltage Controlled Oscillator

VCS
Verilog Compiled Simulator (Synopsys)

VDMA
Video Direct Memory Access

vector

1. The logical state of a set of nodes within a circuit as a function of time.
2. A group of signals that has been renamed for convenience during simulation. It is similar to a bus. "Bus" refers to a group of signals on the schematic, and "vector" refers to a group of signals during simulation.

verification
The process of reading back the configuration data of a device and comparing it to the original design to ensure that all of the design was correctly received by the device.

Verilog
A commonly used Hardware Description Language (HDL) that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. It is defined by IEEE standard 1364-1995. Verilog was originally developed by Cadence Design Systems and is now maintained by OVI.

VHDL
A VHSIC Hardware Description Language. A hardware description language which can be used to describe the concurrent and sequential behavior of a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. VHDL is defined by IEEE standard 1076-1993. A VHDL file has a .vhd or .vhdl extension.

VHSIC
Very High-Speed Integrated Circuit

VITAL
A VHDL Intitiative Toward ASIC Libraries. A VHDL-library standard (IEEE 1076.4) that defines standard constructs for simulation modeling, accelerating, and improving the performance of VHDL simulators.

VLAN
Virtual Local Area Network

VMH file
A file containing a fitted CPLD design.

VSEC
Vendor-Specific Enhanced Capability

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WAC
Write Address Channel Controller

WAN
Wide Area Network

watch list
A list of nodes whose values are to be reported during simulation.

WCDMA
Wideband Code Division Multiple Access

WCOL
Write Collision error

WDC
Write Data Channel Controller

WDT
Watchdog Timer

WF
Write FIFO Register

WFV
Write FIFO Vacancy Register

wide decoder
A wired AND gate.

WiMAX
Worldwide Inter-operability for Microwave Access

wire segment
A metal interconnect track that is physically located on the surface of the chip. Typically connections between two cells use multiple wire segments that are connected together to form an electrical connection.

wired-AND functions
AND gates and their DeMorgan equivalents produced by the inherent structure of the UIM.

wired-AND gate
A symbol, as opposed to a physical gate, representing a function generated from a wired connection of two NAND gates, for example.

wired logic
A wire connection between two gate outputs that provides a specific logic function.

wireload
The maximum number of specified unit loads that a specified output can drive.

WIS
WAN Interface Sublayer

WO
Write Only

WSC
Write Status Controller

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XADC
The XADC block, provided in Xilinx® 7 series FPGAs, includes a dual 12-bit, 1 Mega sample per second (MSPS) analog-to-digital converter and on-chip sensors.

XAUI
eXtended Attachment Unit Interface. A quad transceiver utilizing 3.125 Gbit/second serial links to create a 10 gigabit attachment unit interface. Multiple XAUI interfaces can be implemented to allow a single chip to interface to both 10 Gigabit Ethernet and OC-192c.

XBD File
Xilinx Board Definition file

XCF
The XCF (XST Constraint File) syntax allows you to specify a specific constraint for the entire device (globally) or for specific modules in your design. The syntax is basically the same as the UCF syntax for applying constraints to nets or instances, but with an extension to the syntax to allow constraints to be applied to specific levels of hierarchy. The keyword MODEL defines the entity or module that the constraint will be applied to. If a constraint is applied to an entity or module the constraint will be applied to the each instance of the entity or module.

XCL
Xilinx® CacheLink. A high-performance external memory cache interface available on the MicroBlaze™ processor.

XCO
Xilinx® CORE Generator™ tool log file

XFLOW
A Xilinx command line tool that automates the Xilinx implementation and simulation flows. XFLOW reads a design file as input as well as a flow file and option files.

XGMII
10–Gigabit Media Independent Interface

XGXS
XGMII Extender Sublayer

XilFATfs
LibXil FATFile System. The XilFATfs file system access library provides read/write access to files stored on a CompactFlash or IBM microdrive device.

Xilkernel
The Xilinx embedded kernel, shipped with Xilinx® EDK. A small, extremely modular and configurable RTOS for the Xilinx embedded software platform.

XMD
Xilinx® Microprocessor Debugger

XMK
Xilinx® Microkernel. The entity representing the collective software system comprising the standard C libraries, Xilkernel, Standalone Library, LibXil Memory File System (MFS), LibXil File, and LibXil Drivers.

XMP
Xilinx® Microprocessor Project. This is the top-level project file for a design in Xilinx Platform Studio (XPS).

XPAK
Expansion Pack

XPE
Xilinx® Power Estimator

XPS
Xilinx® Platform Studio. The environment in which you can develop your embedded design.

XPS_LL_TEMAC
XPS LocalLink Tri-Mode Ethernet MAC

XS
Extender Sublayer

XSI
Xilinx® Synopsys Interface. A design tool kit.

XST
Xilinx® Synthesis Technology

XST Command Line
With XST, you can run synthesis in command line mode instead of from the Process window in the Project Navigator. To run synthesis from the command line, you must use the executable file. If you work on a workstation, the name of the executable is "xst".

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yield
The yield is the percentage of defect-free (usable) die on a silicon wafer.

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ZBT
Zero Bus Turnaround