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Memory Interfaces Design Hub - UltraScale DDR3/DDR4 Memory

This page covers Memory Interfacing in UltraScale Devices using the Memory Interface Generator (MIG) in the Vivado Design Suite

IntroductionDate
 Memory Interface UltraScale Design Checklist 
 UltraScale Architecture FPGAs Memory IP Product Guide10/04/2017
 Creating a Memory Interface Design using Vivado MIG10/04/2017
 Designing with UltraScale Memory IP09/16/2014
 Memory Interface UltraScale IP Release Notes06/20/2017
 Supported Memory Interfaces and Data Rates 
Design RequirementsDate
 Input Clock Guidelines10/04/2017
 Memory Interface External Clocking03/15/2016
 PCB Guidelines for DDR4 SDRAM01/30/2017
 PCB Guidelines for DDR3 SDRAM01/30/2017
 DDR4 Pin Rules10/04/2017
 DDR3 Pin Rules10/04/2017
 I/O Planning for UltraScale Device Memory IP10/04/2017
 Designing for High Efficiency10/04/2017
 Calculating User Specified Pattern Efficiency Using the Memory IP Performance Testbench10/04/2017
 Designing with UltraScale Memory IP09/16/2014
 Importing I/O Ports for an Existing Pin-Out/Board10/04/2017
Interfacing to Memory Interface IPDate
 Interfacing to the Memory IP User Interface10/04/2017
 Interfacing to the PHY Only Interface10/04/2017
 Interfacing to the AXI4 Slave Interface10/04/2017
Simulating Memory Interface IPDate
 Simulating the Memory IP Example Design10/04/2017
 Vivado Logic Simulation Design Hub09/07/2017
Frequently Asked Questions (FAQ)Date
 Memory IP UltraScale Solution Center - Frequently Asked Questions (FAQ) 

Additional Learning Materials

Additional Learning Materials

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