Data Center IP

Xilinx SmartCORE IP and LogiCORE™ IP for the Data Center provides system designers a head start on their project with proven, documented IP cores capable of executing a wide range of complex network functions—including traffic management, packet processing, TCP offload, cryptography, compression, and security—and all essential I/O interfaces including 1G/10G/40G/100G Ethernet MACs, PCIe Gen2 and Gen3, XAUI/XLAUI/CAUI, Serial Rapid I/O, SATA, and SAS.

Many of these proven IP cores are configurable so they can be tailored to specific application performance requirements. Xilinx offers specialists and design services to help customers adapt and use this IP to create Generation Ahead equipment designs.

Here is a comprehensive table of all the SmartCORE IP and LogiCore IP specifically used in data-center equipment design.

Data Center IP Cores

Topic Resource Type Provider
Network Traffic Management Traffic Manager
  • 32k queues
  • Five stages
  • SP+DWRR at each stage
SmartCORE IP Xilinx, Inc.
NIC Function TCP Offload Engine
  • Ultra-Low Latency through 10 G TOE = less than 100 ns
  • Sustained large TCP payloads, depending upon remote server/client’s capability
  • 128 Session with scalable Payload FIFO of 8/16/32 K bytes
LogiCORE IP Intiliop
XAUI
  • Designed to 10-Gigabit Ethernet IEEE 802.3-2008 specification
  • Supports 20G double-rate XAUI (Double XAUI)using four transceivers at 6.25 Gb/s under features.
  • Supports 10-Gigabit Fibre Channel (10-GFC) XAUI data rates and traffic
  • Uses four transceivers at 3.125 Gb/s line rate to achieve 10-Gb/s data rate
  • Implements Data Terminal Equipment (DTE)
  • XGMII Extender Sublayer (XGXS), PHY XGXS, and 10GBASE-X Physical Coding Sublayer (PCS)
LogiCORE IP Xilinx, Inc.
Low-latency Ethernet MACs
  • Full 100G and 40G Ethernet line rate operation.
  • Optional Frame Check Sequence (FCS) checking, adding and deleting.
  • Static and dynamic de-skew functions.
  • PCS Lane Marker insertion and deletion.
  • PCS Lane framing and de-framing including swapping of each PCS Lane.
  • Inter-Packet Gap (IPG) insertion and deletion as required by 802.3ba
LogiCORE IP Xilinx, Inc.
Data Security / Compression AES Cryptography
  • Implements AES (Rijndael) to latest NIST FIPS PUB 197
  • Full dynamic support for all AES key sizes (128, 192 and 256-bits)
  • Supports data rates well in excess of 40Gbps
  • Separate cores provided for encryption and decryption
  • Roundkey generation can be split out for ultra low gatecount implementations
  • All AES operating modes easily implemented (eg. ECB, CBC, OFB, CFB, CTR, CCM, GCM, XTS, OCB)
Alliance Member IP Helion Technolgy Ltd.
LZRW3 data compression
  • Implements the LZRW3 lossless data compression algorithm
  • Supports data block sizes from 2K to 32K bytes with data growth protection
  • Completely self-contained; does not require off-chip memory
  • High performance; capable of data throughputs in excess of 1 Gbps
  • Ideal for improving system performance in data comms and storage applications
Alliance Member IP Helion Technolgy Ltd.
IPSEC and MACSEC Security Protocols
  • Performs hardware acceleration of IPsec ESP protocol to RFC 4303
  • Fully configurable to support all mandatory and proposed ESP-v3 confidentiality and integrity algorithms
  • Suitable for use in IPv4 and IPv6 IPsec Transport and Tunnel mode applications
  • Implements Extended (64-bit)
  • Sequence Number for IKEv2 support
  • Supports all ESP security service
  • combinations
  • Supports insertion of padding for
  • Traffic Flow Confidentiality (TFC)
  • Performs automatic ESP padding
  • generation and checking
  • Supports Gigabit/sec throughputs
Alliance Member IP Helion Technolgy Ltd.
System Interconnect QuickPath Interconnect (QPI)
  • Designed for High-speed FPGA-to-processor communications
  • Cache agent, with full-width (20 lanes) operation at 6.4Gbps per lane
  • Example design, for rapid start-up, based on Xilinx® Virtex®-7 FPGA
SmartCORE IP Xilinx Inc.
PCIe Gen2 and Gen3
  • PCI Express™ Base Specification Revision 3.0/2.0/1.1 compliant
  • x1, x2, x4, x8, x16 lane support
  • 8.0, 5.0 & 2.5 Gbit/s SERDES suppor
  • Endpoint and Root Port support
  • 32, 64, 128 and 256 bit Core widths to enable user to match core speed with process capability
  • AER, ECRC, MSI-X, Multi-Vector MSI, Lane Reversal support
Alliance Member IP Northwest Logic, PLDA
Storage Interface Serial ATA (SATA)
  • Fully compliant to the SATA 1.5Gb/s, 3.0Gb/s, and 6.0Gb/s industry specifications
  • Transport or AHCI or Application or Application Register (ARI) interface options
  • Data Interface through FIFOs
  • Supports either Seres, PIPE, or SAPIS interface
Alliance Member IP Intelliprop Inc.
Serial Attached SCSI (SAS)
  • Fully compliant to the SAS 6.0Gb/s industry specifications
  • AHB-Lite and FPGA specific interfaces for register access
  • Supports either SERDES or PHY layer interface
Fully verified with SAS Verification IP
Alliance Member IP Intelliprop Inc.
 
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