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Using Virtex-5 FPGAs in Your Wired Solutions

Use the Virtex-5 FPGA Across the Networking Linecard

To meet the challenges of converged IP-based networks for voice, video, and data, Virtex®-5 FPGAs can help you build advanced packet processing functions, telecom framer/MAC blocks, wired access framers/MACs, serial backplane interfaces and other wired communications system functions such as memory controllers, embedded subsystems, and protocol bridging.

Figure 1

Programmable Telecom/Datacom linecard based on Virtex-5 FPGAs.

The Virtex-5 FPGA provides high performance, flexibility and scalability with unique, cost-optimized platforms built on the following features:

High-density, high-speed, reprogrammable ExpressFabric architecture

  • Creates and integrate of Layer 1 - Layer 7 protocol processing blocks.
  • Implements packet processing functions with unique or proprietary algorithms (Traffic Management).
  • Supports wire-speed throughput.
  • Interconnect a combination of FPGA, ASIC, ASSPs, NPUs, CPUs, DSPs and memories with disparate protocols.
  • Provides protocol bridging support, such as ATM to Ethernet.
  • Maximizes utility by enabling programmable networking hardware.
  • Improved 6-input LUT design enables further efficiencies in functional block implementations.

550Mhz 36 Kbit Dual-Port Block RAM / FIFO

  • Accesses internal memory resources quickly.
  • Reduces BOM and requirements for external memory when creating FIFOs and packet buffers.
  • Increased BRAM-Logic ratio on SXT devices targets block RAM intensive applications such as packet processing.

550 Mhz 25x18 DSP slice

  • Accelerates communications algorithms such as the Fairness algorithm in RPR.
  • Saves valuable logic resources for other functions.
  • Increased number of DSP slice to logic ratio on SXT devices make it ideal for math intensive applications like FEC.
  • Lowest cost per-channel FEC.

550Mhz Clock Management Tile (CMT)

  • Designs high throughput applications with faster operating frequencies.
  • Develops highly integrated System on a Chip designs with multiple clock domains.
  • Reduces difficulties in system-level board design using multiple reference clocks.

SelectIO Technology

  • Ensures highest possible throughput across standard/proprietary single-ended interfaces such as HSTL and SSTL, and differential interfaces such as SFI-4 and SPI4.2.
  • Interconnects a combination of FPGA, ASIC, ASSPs, NPUs, CPUs, DSPs and memories with disparate protocols.

High-Speed GTP Transceivers (Virtex-5 LXT/ SXT/FXT/TXT)

  • Replaces existing external transceivers reducing system power and cost
  • 100Mbps – 6.5Gbps operational range
  • Lowest power consumption in the industry at <100 mW at 3.2 Gbps and <200 mW at 6.5 Gbps
  • Provide high speed and high count I/Os to support for the inter-chip and inter-board communication protocols such as Interlaken, HiGIG, RXAUI, SPAUI
  • Embedded PCI Express and Tri-mode Ethernet MAC blocks

Reduced Power Consumption

  • Eases power management design, particularly for rack mounted systems.
  • Uses System Monitor for voltage and temperature control, analysis and alarms.
  • Reduces power management costs associated with airflow, fans and heat sinks.

Sparse Chevron Package

  • Enables reliable high-speed I/O performance and design margin for demanding parallel I/O applications, including memory and standard interfaces such as GMII and SPI4.2.
Virtex-5 FPGA Wired Communications Applications
Category Application
Packet Processing
  • Traffic Management
  • Classification
  • Packet Editing
  • Data and Network Security
  • TCP/IP Offload
Telecom Framers & MACs
  • SONET/SDH Framers/Mappers
  • PDH Framers / Mappers
  • POS, ATM Mappers
  • ATM - AALx, SAR,
  • Ethernet over SONET (EOS) - GFP, VCAT, LCAS
  • 1GE, 10GE, 40GE, 100GE MAC
  • G.709 OTN
  • Pseudowire (PWE3)
  • RPR
  • L1/L2 Switching
Wired Access (DSL, PON, CMTS)
  • xPON MAC
  • ATM-to-Ethernet Interworking
  • Inverse Multiplexing over ATM (IMA)
Serial Backplanes & Bridging (chip-to-chip, chip-to-module, chip to backplane)
  • XAUI / HiGIG+/RXAUI/10GE/ Interlaken
  • Gigabit Ethernet (soft or hard MAC)
  • Serial RapidIO
  • PCI-Express (Soft or hard PCIe® system block
  • TFI-5
  • OC-48
  • Aurora (lightweight serial protocol)
  • Proprietary 600 Mbps to 3.2 Gbps
  • Mesh Fabric Interface
  • AdvancedTCA/ MicroTCA
  • Bridges such as SPI-4.2 to XAUI and SFI-4.1 to TFI-5
  • Framer to Lineside PHY (SFI-4.1/XSBI/XAUI)
  • Proprietary interfaces
  • And more
Memory Controllers
  • DDR2 SDRAM, DDR SDRAM, QDR II SRAM, RLDRAM II, DDR3
Embedded Processing (MicroBlaze™ soft processor)
  • In-FPGA, hardware/software partitioning
  • Packet Processing
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