Wired Networking IP, Reference Designs and Documentation

Smarter Solutions

From the Network Core to the Edge, Xilinx SmartCORE IP and LogiCORE™ IP provides the critical head start for your next project with proven IP cores that address a broad spectrum of network functions and applications. SmartCORE IP for OTN includes state-of-the art Framer, Mapper, Overhead Processor, SAR and FEC cores. SmartCORE IP for Packet Based Processing includes the essential, packet processing and traffic management capabilities to address Core Routing /Switching, Software Defined Networking, Next Generation Routing and “Quad-Play” applications. SmartCORE IP for Access, Backhaul and System Connectivity address next generation network requirements including: PWE3, xPON MAC, 1588 Timing and industry leading connectivity including Interlaken and PCIe. The Xilinx SmartCore IP portfolio is supplemented by a rich suite of IP cores available from Xilinx partners yielding a solutions portfolio that is unmatched in the industry.

Backhaul and Access Network
Connectivity
OTN
Packet-Based Processing

Backhaul and Access Network
Topic	Resource	Type	Provider
Backhaul and Access	Wired Backhaul and/or NID Solution Integration of IP Blocks and Software in AP Zynq SoC Scalable from 5Gbps to greater than 20Gbps forwarding throughput Flexible protocol configuration and termination Combines Switching, Packet Processing, Traffic Management/QoS, Packet timing and Synchronization, PWE3 in a single design Conforms to MEF specifications For further information please contact your local Sales Representative for access to the Backhaul and Access Lounge.	SmartCORE IP	Xilinx, Inc.
	PWE3 Supports from 4 x T1/E1 to 4x OC3/STM1 SAToP CESoPSN TDMoIP E1 to VC12 to Demmaper/Mapper DDR2 or DD3 for external memory Smallest footrpint For further information please contact your local Sales Representative for access to the Backhaul and Access Lounge.	Partner IP	CXT
	PON MAC 1G and 10G EPON Integrated BCDR OLT and ONT/ONU MAC IEEE 802.3ah and IEEE 802.3av compliant 128-bit AES encryption Hardware DBA implement in programmable logic IEEE 802.3 ah MPCP DDR3 memory For further information please contact your local Sales Representative for access to the Backhaul and Access Lounge.	Partner IP	CXT
	1588v2 1588v2 compliant Ordinary Clock (OC) 1588v2 compliant Boundary Clock (BC) 1588v2 Compliant Transparent Clock (TC) Single Chip Solution with small footprint Hybrid 1588v2/SyncE supported Flexible reference clock input: 1pps, 1.544MHz, 2.048Mhz, 10Mhz, or 25Mhz TCXO or OCXO ToD better than +/-1usec on managed 10-GE Switched network per ITU-G.8261 Frequency accuracy better than 16ppb on managed 10-GE Switched network per ITU-G.8261 Integrated PTP and Servo on same chip DDR3 memory For further information please contact your local Sales Representative for access to the Backhaul and Access Lounge.	Partner IP	IPClock

Connectivity
Topic	Resource	Type	Provider
MAC to Interlaken Bridges	10x10G or 100G to 120G MAC to 120G Interlaken Bridge 10BASE-R PHY for 10x10GE configuration 100G CAUI PHY for 100GE configuration Pause Frame Flow Control PCIe x1 interface Statistics registers On Chip loopback 120G Interlaken Interface Interlaken revision 1.2 12 x 10.3125 per lane Per channel flow control Fixes channel mapping to Ethernet Error Handling Partial packet drop Error packet drop Independent reset control per port On-chip voltage and temperature monitoring For further information please contact your local Sales Representative for access to the Lounge.	SmartCORE IP	Xilinx, Inc.

OTN
Topic	Resource	Type	Provider
OTN	OTU4 Framer Bit/Byte Alignment LOF, LOM & Gen AIS detection Overhead Insertion & Extraction ODU4 AIS/LCK Generation For further information please contact your local Sales Representative for access to the OTN Lounge.	SmartCORE IP	Xilinx, Inc.
	OTL4.10 Operates in accordance with the ITU-T G.709/Y.1331 (12/2009) and ITU-T G.798 (10/2010) standards Receiver accommodates lane deskew of up to 500ns Loss-of-Lane-Alignment defect output for signalling forward to downstream blocks, based on G.798/G.709. Automatically adapts to changes in incoming lane ordering For further information please contact your local Sales Representative for access to the OTN Lounge.	SmartCORE IP	Xilinx, Inc.
	100GbE to ODU4 Mapper Fully ITU-T G.709 compliant Comprehensive ODU4 overhead processing including six levels of tandem connection monitoring (TCM), when used in conjunction with the external overhead processor Automatic client and ODU4 replacement signal generation in the event of a fault detection Exports generic mapping procedure (GMP) Cn timing information to allow external clock regeneration For further information please contact your local Sales Representative for access to the OTN Lounge.	SmartCORE IP	Xilinx, Inc.
	100G XOHP 128ch Overhead Processor ITU-T G.709 compliant OH Generation and Termination/Monitoring SM, PM and TCM[1-6] Overhead processing TTI, DEG, IAE, BDI, BEI, BIAE, LTC, AIS, OCI, LCK support Near and Far End EBC Performance Monitors APS Acceptance Payload Monitoring, PLM, MSIM, CSF SNC Defects, SSF, SSD, TSF and TSD FTFL support Consequent Actions support For further information please contact your local Sales Representative for access to the OTN Lounge.	SmartCORE IP	Xilinx, Inc.
	100G Single Stage Mux ODU0,1,2,2e,3 and Flex support ODU4 Bypass support GMP Rate Adaption Type 21 Multiplexing ODU4 Term/Gen ODU4 BIP8 Calculation. ODU4 PM and TCM1-6 Term/Gen ODU4 OMFI and PSI/MSI ODUj Framing, LOFLOM and MSIM For further information please contact your local Sales Representative for access to the OTN Lounge.	SmartCORE IP	Xilinx, Inc.
	100G ODUk Mon Uni-directionally monitor up to 80 channels with a maximum bandwidth of 100G Any combination of ODUkL traffic -ODU0,1,2,2e,3,4 and Flex traffic Extracts PM and TCM 1-6 overheads Supports override of any onward traffic Supports replacement of onward traffic For further information please contact your local Sales Representative for access to the OTN Lounge.	SmartCORE IP	Xilinx, Inc.
	100G SAR OIF Compatible SAR maps ODUk TDM traffic in to packetized ODUk (pODUk) flows Facilitates OTN Switching across packet switches Supports 0,1,2,2e,3,4 and Flex traffic Supports pODUk fabric ingress squelch Supports CSI propagation For further information please contact your local Sales Representative for access to the OTN Lounge.	SmartCORE IP	Xilinx, Inc.
	ITU G.709 GFEC Support for OTU1, OTU2, OTU3 and OTU4 line rates Designed to minimize size and latency Standardized AXI-4 interface for ease of design Software interface is similar across line rates and FEC types to maximize software reuse across designs Common detailed statistics bus for all FEC types Supplied with extended statistics reference design For further information please contact your local Sales Representative for access to the OTN Lounge.	SmartCORE IP	Xilinx, Inc.
	10G I.4 EFEC Compliant to G.795.1 – I.4 for interoperability with deployed equipment Designed to minimize size and latency Standardized AXI-4 interface for ease of design Software interface is similar across line rates and FEC types to maximize software reuse across designs For further information please contact your local Sales Representative for access to the OTN Lounge.	SmartCORE IP	Xilinx, Inc.
	10G I.7 EFEC Compliant to G.795.1 – I.7 for interoperability with deployed equipment Designed to minimize size and latency Standardized AXI-4 interface for ease of design Software interface is similar across line rates and FEC types to maximize software reuse across designs For further information please contact your local Sales Representative for access to the OTN Lounge.	SmartCORE IP	Xilinx, Inc.
	100G XFEC High Gain 100G FEC with coding gain >9.35dB at 7% overhead Designed to minimize size and latency Standardized AXI-4 interface for ease of design Software interface is similar across line rates and FEC types to maximize software reuse across designs Common detailed statistics bus for all FEC types For further information please contact your local Sales Representative for access to the OTN Lounge.	SmartCORE IP	Xilinx, Inc.
	OTN Framer Supports OTU1-OTU4 line rates Conforms to G.709 G.709 FEC (GFEC) and optional EFEC support Processes OTUk, ODUk and OPUk overhead Supports synchronous (ATM, GFP) and asynchronous (SONET/SDH) payload mapping (accommodating positive/negative stuffing)	Alliance Partner IP	Aliathon
	Forward Error Correction Supports OTU1-OTU4 line rates Conforms to G.709 (GFEC), G.975.1 (EFEC) and proprietary schemes OH: 7% - 20%+ NECG: 6.3db - 9.35db (7% OH)	Alliance Partner IP	Aliathon
	ODU Mux Supports G.708 Muxing of client ODU0/1/2/3 signals into ODU1/2/3/4 Full OTN overhead processing for intermediate stages 1 and 2 stage mux/demux functionality	Alliance Partner IP	Aliathon
	GMP (Generic Mapping Procedure) Supports G.708 Muxing of client ODU0/1/2/3 signals into ODU1/2/3/4 Full OTN overhead processing for intermediate stages 1 and 2 stage mux/demux functionality	Alliance Partner IP	Aliathon
	2.5G GFP-F (Framer) Compliant with ITU-T G.7041 specification Generates/Synchronizes to GFP data stream including IDLE frames Provides GFP scrambling/descrambling Full Overhead and Defect processing	Alliance Partner IP	Aliathon
	10G GFP-F (Framer) Compliant with ITU-T G.7041 specification Generates/Synchronizes to GFP data stream including IDLE frames Provides GFP scrambling/descrambling Full Overhead and Defect processing	Alliance Partner IP	Aliathon
	GFP-T (Transparent) Compliant with ITU-T G.7041 specification Encodes input blocks into 67 byte GFP-T blocks as per G.7041 Extracts 64 byte 8B/10B blocks of data from GFP-T frames.	Alliance Partner IP	Aliathon
	100G OTN Muxponder Conforms to G.709 OTU4 line side interface (OTL4.10) supporting GFEC & proprietary eFEC schemes GFEC (6.7% NECG @ ~7% overhead) eFEC (CI-BCH providing 9.35db NECG @ ~7% overhead) OTU2/2e/1e, STM64/OC192 & 10GbE client rates supported OTU2 client configures for GFEC or G.975.1 appendix I.4 or I.7 eFEC 10G Clients mapped via ODU2 to ODU4 payload via GMP. Direct access to core registers for rapid software development Errors, defects & stats provided for all client & line signals via MicroBlaze uProcessor ref design	Alliance Partner IP	Aliathon
	100G OTN Transponder Conforms to G.709 OTU4 line side interface (OTL4.10) supporting GFEC & proprietary eFEC schemes GFEC (6.7% NECG @ ~7% overhead) eFEC (CI-BCH providing 9.35db NECG @ ~7% overhead) 100Gb Ethernet client side Bulk mapped to ODU4 via GMP Direct access to core registers for rapid software development Errors, defects & stats provided for all client & line signals via MicroBlaze uProcessor ref design	Alliance Partner IP	Aliathon
	100G OTN Repeater/Regenerator Conforms to G.709 OTU4 line side interface (OTL4.10) supporting GFEC & proprietary eFEC schemes GFEC (6.7% NECG @ ~7% overhead) eFEC (CI-BCH providing 9.35db NECG @ ~7% overhead) Direct access to core registers for rapid software development	Alliance Partner IP	Aliathon
	40G OTN Muxponder Conforms to G.709 OTU3 line side interface (OTL3.4) supporting GFEC. GFEC (6.7% NECG @ ~7% overhead) OTU2/2e/1e, STM64/OC192 & 10GbE client rates supported OTU2 client configures for GFEC or G.975.1 appendix I.4 or I.7 eFEC 10G Clients mapped via ODU2 to ODU3 payload via GMP. LAN, WIS etc. as per ITU-T G.Sup43 Transcoding of 10GFC Transparent mapping of 10G SDH clients Direct access to core registers for rapid software development	Alliance Partner IP	Aliathon
	40G OTN Transponder Conforms to G.709 OTU3 line side interface (OTL3.4) supporting GFEC. GFEC (6.7% NECG @ ~7% overhead) 40Gb Ethernet client side transcoded to ODU3 Direct access to core registers for rapid software development	Alliance Partner IP	Aliathon

Packet-Based Processing
Topic	Resource	Type	Provider
Packet-Based Processing	Traffic Management IP Suite Unified architecture scalable across bandwidth 10Gbps to 100Gbps (200 Gbps upcoming) and number of queues from 2K to 64K) Support for min Ethernet packet size (at full line-rate) and jumbo frames. Scalable architecture enabling up to 5 levels of scheduling hierarchy, where each level could be independently configured with policing, shaping, scheduling and congestion/flow control features. Congestion control: TD, RED, and WRED Flow control -per queue/per aggregate of queues/per hierarchy. Scheduling: SP, Deficit Weighted Round Robin(DWRR), patent pending SP+ (for optimal combination of scheduling functions) Policing: discard or marking based on srTCM, trTCM, and mefTCM, For further information please contact your local Sales Representative for access to the PPTM Lounge.	SmartCORE IP	Xilinx, Inc.
Packet-Based Processing	Programmable Packet Parser L2-L7 protocol parsing Intuitive declarative language speeds packet parsing including header and payload. Suite of advanced compilation tools enabling generation of RTL that is tuned to Xilinx FPGA architecture Parser output must be processed by Xilinx FPGA tool chain (ISE or Vivado) Parser can examine data streams of any length with fixed or variable space between sequential fields. For further information please contact your local Sales Representative for access to the PPTM Lounge.	SmartCORE IP	Xilinx, Inc.