Wired Networking IP, Reference Designs and Documentation

From the Network Core to the Edge, Xilinx SmartCORE IP and LogiCORE™ IP provides the critical head start for your next project with proven IP cores that address a broad spectrum of network functions and applications. SmartCORE™ IP for OTN includes state-of-the art Framer, Mapper, Overhead Processor, SAR and FEC cores. The Specification Design Environment for Networking (SDNet) in addition to the SmartCORE IP for Packet Based Processing provides the essential, packet processing and traffic management capabilities to address Core Routing /Switching, Software Defined Networking (SDN), Softly Defined Networks, Next Generation Routing, Network Functions Virtualization (NFV) and “Quad-Play” applications. SmartCORE IP for Access, Backhaul and System Connectivity address next generation network requirements including: PWE3, xPON MAC, 1588 Timing and industry leading connectivity including Interlaken and PCIe. The Xilinx SmartCore IP portfolio is supplemented by a rich suite of IP cores available from Xilinx partners yielding a solutions portfolio that is unmatched in the industry.

Backhaul and Access Network
Topic Resource Type Provider
Backhaul and Access Wired Backhaul and/or NID Solution
  • Integration of IP Blocks and Software in AP Zynq SoC
  • Scalable from 5Gbps to greater than 20Gbps forwarding throughput
  • Flexible protocol configuration and termination
  • Combines Switching, Packet Processing, Traffic Management/QoS, Packet timing and Synchronization, PWE3 in a single design
  • Conforms to MEF specifications
For further information please contact your local Sales Representative for access to the Backhaul and Access Lounge.
SmartCORE IP Xilinx, Inc.
PWE3
  • Supports from 4 x T1/E1 to 4x OC3/STM1
  • SAToP
  • CESoPSN
  • TDMoIP
  • E1 to VC12 to Demmaper/Mapper
  • DDR2 or DD3 for external memory
  • Smallest footrpint
For further information please contact your local Sales Representative for access to the Backhaul and Access Lounge.
Alliance Member IP CXT
PON MAC
  • 1G and 10G EPON
  • Integrated BCDR
  • OLT and ONT/ONU MAC
  • IEEE 802.3ah and IEEE 802.3av compliant
  • 128-bit AES encryption
  • Hardware DBA implement in programmable logic
  • IEEE 802.3 ah MPCP
  • DDR3 memory
For further information please contact your local Sales Representative for access to the Backhaul and Access Lounge.
Alliance Member IP CXT
1588v2
  • 1588v2 compliant Ordinary Clock (OC)
  • 1588v2 compliant Boundary Clock (BC)
  • 1588v2 Compliant Transparent Clock (TC)
  • Single Chip Solution with small footprint
  • Hybrid 1588v2/SyncE supported
  • Flexible reference clock input: 1pps, 1.544MHz, 2.048Mhz, 10Mhz, or 25Mhz
  • TCXO or OCXO
  • ToD better than +/-1usec on managed 10-GE Switched network per ITU-G.8261
  • Frequency accuracy better than 16ppb on managed 10-GE Switched network per ITU-G.8261
  • Integrated PTP and Servo on same chip
  • DDR3 memory
For further information please contact your local Sales Representative for access to the Backhaul and Access Lounge.
Alliance Member IP IPClock Ltd.
Connectivity
Topic Resource Type Provider
MAC to Interlaken Bridges 10x10G or 100G to 120G MAC to 120G Interlaken Bridge
  • 10BASE-R PHY for 10x10GE configuration
  • 100G CAUI PHY for 100GE configuration
  • Pause Frame Flow Control
  • PCIe x1 interface
  • Statistics registers
  • On Chip loopback
  • 120G Interlaken Interface
    • Interlaken revision 1.2
    • 12 x 10.3125 per lane
    • Per channel flow control
    • Fixes channel mapping to Ethernet
  • Error Handling
    • Partial packet drop
    • Error packet drop
  • Independent reset control per port
  • On-chip voltage and temperature monitoring
For further information please contact your local Sales Representative for access to the Lounge.
SmartCORE IP Xilinx, Inc.

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OTN
Topic Resource Type Provider
OTN 4x100G Transponder
  • High density single chip OTN transport solution
  • Four independent 100GbE to OTL4.10 Transponder with GFEC
  • OH processor supporting SM, PM and six levels of TCM
  • PHY solution removes the need for external PLL
  • Automatic OTN consequent actions & client replacement
  • Optimized design uses 63% LUTs and 37% BRAMs of a Virtex-7 (XC7V1140T) allowing additional customer IP for product differentiation
  • Comprehensive OS Agnostic Software APIs for simplified integration
  • Graphical user interface to configure and display device status, defects and performance monitors to acclerate evaluation
  • XCLI application for customer application development and infield support
For further information please contact your local Sales Representative for access to the OTN Lounge.
Reference Design Xilinx, Inc.
2x100G Switching
  • High density single chip OTN switching solution
  • Lane 1 - OTL4.10 to pODUj MuxSAR
    • Support for any combination of upto 80 ODUp channels with a maximum bandwidth of an ODU4
    • Any ODUj to ODU4 100G One Stage Mutilplexing
  • Lane 2 - 100GbE to pODU4 MapSAR
  • 100G OIF compliant SAR
  • Interlaken Interface
  • OH processor supporting SM, PM and six levels of TCM
  • PHY solution removes the need for external PLL
  • Automatic OTN consequent actions and client replacement
  • Optimized design uses 63% LUTs and 37% BRAMs of a Virtex-7 (XC7V1140T) allowing additional customer IP for product differentiation
  • Comprehensive OS Agnostic Software APIs for simplified integration
  • Graphical user interface to configure and display device status, defects and performance monitors to acclerate evaluation
  • XCLI application for customer application development and infield support
For further information please contact your local Sales Representative for access to the OTN Lounge.
Reference Design Xilinx, Inc.
OTU4 Framer
  • Bit/Byte Alignment
  • LOF, LOM & Gen AIS detection
  • Overhead Insertion & Extraction
  • ODU4 AIS/LCK Generation
For further information please contact your local Sales Representative for access to the OTN Lounge.
SmartCORE IP Xilinx, Inc.
OTL4.10
  • Operates in accordance with the ITU-T G.709/Y.1331 (12/2009) and ITU-T G.798 (10/2010) standards
  • Receiver accommodates lane deskew of up to 500ns
  • Loss-of-Lane-Alignment defect output for signalling forward to downstream blocks, based on G.798/G.709.
  • Automatically adapts to changes in incoming lane ordering
For further information please contact your local Sales Representative for access to the OTN Lounge.
SmartCORE IP Xilinx, Inc.
100GbE to ODU4 Mapper
  • Fully ITU-T G.709 compliant
  • Comprehensive ODU4 overhead processing including six levels of tandem connection monitoring (TCM), when used in conjunction with the external overhead processor
  • Automatic client and ODU4 replacement signal generation in the event of a fault detection
  • Exports generic mapping procedure (GMP) Cn timing information to allow external clock regeneration
For further information please contact your local Sales Representative for access to the OTN Lounge.
SmartCORE IP Xilinx, Inc.
100G XOHP 128ch Overhead Processor
  • ITU-T G.709 compliant OH Generation and Termination/Monitoring
  • SM, PM and TCM[1-6] Overhead processing
  • TTI, DEG, IAE, BDI, BEI, BIAE, LTC, AIS, OCI, LCK support
  • Near and Far End EBC Performance Monitors
  • APS Acceptance
  • Payload Monitoring, PLM, MSIM, CSF
  • SNC Defects, SSF, SSD, TSF and TSD
  • FTFL support
  • Consequent Actions support
For further information please contact your local Sales Representative for access to the OTN Lounge.
SmartCORE IP Xilinx, Inc.
100G Single Stage Mux
  • ODU0,1,2,2e,3 and Flex support
  • ODU4 Bypass support
  • GMP Rate Adaption
  • Type 21 Multiplexing
  • ODU4 Term/Gen
  • ODU4 BIP8 Calculation.
  • ODU4 PM and TCM1-6 Term/Gen
  • ODU4 OMFI and PSI/MSI
  • ODUj Framing, LOFLOM and MSIM
For further information please contact your local Sales Representative for access to the OTN Lounge.
SmartCORE IP Xilinx, Inc.
100G ODUk Mon
  • Bi-directionally monitor  up to 80 channels with a  maximum bandwidth of 100G
  • Any combination of ODUkL traffic -ODU0,1,2,2e,3,4 and Flex traffic
  • Extracts PM and TCM 1-6 overheads
  • Supports override of any onward traffic
  • Supports replacement of onward traffic
For further information please contact your local Sales Representative for access to the OTN Lounge.
SmartCORE IP Xilinx, Inc.
100G SAR
  • OIF Compatible SAR maps ODUk TDM traffic in to packetized ODUk (pODUk) flows
  • Facilitates OTN Switching across packet switches
  • Supports 0,1,2,2e,3,4 and Flex traffic
  • Supports pODUk fabric ingress squelch
  • Supports CSI propagation
For further information please contact your local Sales Representative for access to the OTN Lounge.
SmartCORE IP Xilinx, Inc.
ITU G.709 GFEC
  • Support for OTU1, OTU2, OTU3 and OTU4 line rates
  • Designed to minimize size and latency
  • Standardized AXI-4 interface for ease of design
  • Software interface is similar across line rates and FEC types to maximize software reuse across designs
  • Common detailed statistics bus for all FEC types
  • Supplied with extended statistics reference design
For further information please contact your local Sales Representative for access to the OTN Lounge.
SmartCORE IP Xilinx, Inc.
10G I.4 EFEC
  • Compliant to G.795.1 – I.4 for interoperability with deployed equipment
  • Designed to minimize size and latency
  • Standardized AXI-4 interface for ease of design
  • Software interface is similar across line rates and FEC types to maximize software reuse across designs
For further information please contact your local Sales Representative for access to the OTN Lounge.
SmartCORE IP Xilinx, Inc.
10G I.7 EFEC
  • Compliant to G.795.1 – I.7 for interoperability with deployed equipment
  • Designed to minimize size and latency
  • Standardized AXI-4 interface for ease of design
  • Software interface is similar across line rates and FEC types to maximize software reuse across designs
For further information please contact your local Sales Representative for access to the OTN Lounge.
SmartCORE IP Xilinx, Inc.
100G XFEC
  • High Gain 100G FEC with coding gain >9.35dB at 7% overhead
  • Designed to minimize size and latency
  • Standardized AXI-4 interface for ease of design
  • Software interface is similar across line rates and FEC types to maximize software reuse across designs
  • Common detailed statistics bus for all FEC types
For further information please contact your local Sales Representative for access to the OTN Lounge.
SmartCORE IP Xilinx, Inc.
OTN Framer
  • Supports OTU1-OTU4 line rates
  • Conforms to G.709
  • G.709 FEC (GFEC) and optional EFEC support
  • Processes OTUk, ODUk and OPUk overhead
  • Supports synchronous (ATM, GFP) and asynchronous (SONET/SDH) payload mapping (accommodating positive/negative stuffing)
Alliance Member IP Aliathon
Forward Error Correction
  • Supports OTU1-OTU4 line rates
  • Conforms to G.709 (GFEC), G.975.1 (EFEC) and proprietary schemes
  • OH: 7% - 20%+
  • NECG: 6.3db - 9.35db (7% OH)
Alliance Member IP Aliathon
ODU Mux
  • Supports G.708 Muxing of client ODU0/1/2/3 signals into ODU1/2/3/4
  • Full OTN overhead processing for intermediate stages
  • 1 and 2 stage mux/demux functionality
Alliance Member IP Aliathon
GMP (Generic Mapping Procedure)
  • Supports G.708 Muxing of client ODU0/1/2/3 signals into ODU1/2/3/4
  • Full OTN overhead processing for intermediate stages
  • 1 and 2 stage mux/demux functionality
Alliance Member IP Aliathon
2.5G GFP-F (Framer)
  • Compliant with ITU-T G.7041 specification
  • Generates/Synchronizes to GFP data stream including IDLE frames
  • Provides GFP scrambling/descrambling
  • Full Overhead and Defect processing
Alliance Member IP Aliathon
10G GFP-F (Framer)
  • Compliant with ITU-T G.7041 specification
  • Generates/Synchronizes to GFP data stream including IDLE frames
  • Provides GFP scrambling/descrambling
  • Full Overhead and Defect processing
Alliance Member IP Aliathon
GFP-T (Transparent)
  • Compliant with ITU-T G.7041 specification
  • Encodes input blocks into 67 byte GFP-T blocks as per G.7041
  • Extracts 64 byte 8B/10B blocks of data from GFP-T frames.
Alliance Member IP Aliathon
100G OTN Muxponder
  • Conforms to G.709
  • OTU4 line side interface (OTL4.10) supporting GFEC & proprietary eFEC schemes
  • GFEC (6.7% NECG @ ~7% overhead)
  • eFEC (CI-BCH providing 9.35db NECG @ ~7% overhead)
  • OTU2/2e/1e, STM64/OC192 & 10GbE client rates supported
  • OTU2 client configures for GFEC or G.975.1 appendix I.4 or I.7 eFEC
  • 10G Clients mapped via ODU2 to ODU4 payload via GMP.
  • Direct access to core registers for rapid software development
  • Errors, defects & stats provided for all client & line signals via MicroBlaze uProcessor ref design
Alliance Member IP Aliathon
100G OTN Transponder
  • Conforms to G.709
  • OTU4 line side interface (OTL4.10) supporting GFEC & proprietary eFEC schemes
  • GFEC (6.7% NECG @ ~7% overhead)
  • eFEC (CI-BCH providing 9.35db NECG @ ~7% overhead)
  • 100Gb Ethernet client side
  • Bulk mapped to ODU4 via GMP
  • Direct access to core registers for rapid software development
  • Errors, defects & stats provided for all client & line signals via MicroBlaze uProcessor ref design
Alliance Member IP Aliathon
100G OTN Repeater/Regenerator
  • Conforms to G.709
  • OTU4 line side interface (OTL4.10) supporting GFEC & proprietary eFEC schemes
  • GFEC (6.7% NECG @ ~7% overhead)
  • eFEC (CI-BCH providing 9.35db NECG @ ~7% overhead)
  • Direct access to core registers for rapid software development
Alliance Member IP Aliathon
40G OTN Muxponder
  • Conforms to G.709
  • OTU3 line side interface (OTL3.4) supporting GFEC.
  • GFEC (6.7% NECG @ ~7% overhead)
  • OTU2/2e/1e, STM64/OC192 & 10GbE client rates supported
  • OTU2 client configures for GFEC or G.975.1 appendix I.4 or I.7 eFEC
  • 10G Clients mapped via ODU2 to ODU3 payload via GMP.
  • LAN, WIS etc. as per ITU-T G.Sup43
  • Transcoding of 10GFC
  • Transparent mapping of 10G SDH clients
  • Direct access to core registers for rapid software development
Alliance Member IP Aliathon
40G OTN Transponder
  • Conforms to G.709
  • OTU3 line side interface (OTL3.4) supporting GFEC.
  • GFEC (6.7% NECG @ ~7% overhead)
  • 40Gb Ethernet client side transcoded to ODU3
  • Direct access to core registers for rapid software development
Alliance Member IP Aliathon

ITU G.709 Framers: XCO0, XCO1, XCO2, XCO3, XCO4, XCO2F, XCO3F, XCO4F, XCO23

  • Support for OTU1, OTU2, OTU3 and OTU4 line rates
  • Supports fixed and flex framing
  • Complies with ITU-T G.709 and ITU-T G.798 specifications
  • Flexible insertion and extraction of OTUk, ODUk, and OPUk overhead byte information
Alliance Member IP Xelic, Inc.

OTL Line Interface Framers: XCO3AU, XCO23AU, XCO4AU

  • Supports OTL3.4, OTL4.4 and OTL4.10 formats.
  • XCO23 supports both 40G and 4 x 10G OTN
  • Complies with ITU-T G.709 and ITU-T G.798 specifications
  • Many configurable options allow for resource utilization optimization.
Alliance Member IP Xelic, Inc.

ITU G.709 GFEC’s: XCO23GFEC,XCO2GFEC,  XCO3GFEC, XCO4GFEC

  • Support for OTU2, OTU3 and OTU4 line rates
  • XCO23GFEC supports both 40G and 4 x 10G OTN
  • Provides statistics per lane in case of OTL3.4 and OTL 4.10 and per stream in case of 4x10G mode.
  • Provides corrected symbols, corrected codeword, and uncorrected codeword outputs
Alliance Member IP Xelic, Inc.

ITU G.975 EFEC’s: XCO2EFEC4, XCO2EFEC7, XCO2EFEC47

  • Support for OTU2 line rate
  • Fully interoperable with all industry standard ASSP’s and equipment.
  • Provides corrected ones and corrected zeroes outputs, embedded scrambler is used to give optic line values.
  • Provides uncorrected codeword outputs
Alliance Member IP Xelic, Inc.

ITU G.709 and G.798 Multiplexors: XCO01MX, XCO12MX, XCO13MX, XCO23MX

  • Support for ODU0 to ODU3 rates
  • Complies with ITU-T G.709 and ITU-T G.798 specifications
  • Automatic justification control is provided based on programmable FIFO thresholds or incoming PJ/NJ request signaling.
  • Flexible OPU overhead field insertion provided
Alliance Member IP Xelic, Inc.

ITU G.709 and G.798 Flex Multiplexors: XCO2FMX, XCO3FMX, XCO4FMX

  • Performs tributary timeslot interleaving and switching of independent ODU0, ODU1, ODU1e, ODU2, ODU2e, ODU3, and ODU Flex data streams
  • Complies with ITU-T G.709 and ITU-T G.798 specifications.
  • Incoming ODUk data streams are distributed over 1 or more 1.25G timeslots using generic mapping
  • Flexible OPU overhead field insertion is provided with PT 20 and PT 21 support
Alliance Member IP Xelic, Inc.

100G Packet Processing: XCG4FM, XCO4SAR, XCI4FIC

  • XCO4GFP - Compliant with ITU G.Sup43 and G.7041/Y.1308 Specifications
  • XCO4GFP - Contains Time Sliced architecture for GFP frame mapped Transmit and Receive processors supporting 80/96 slice 100G/120G OTN applications with support for up to 256 slices
  • XCO4SAR - Complies with IA OIF-OFP-01.0 specification
  • XCO4SAR - Accepts incoming ODUk/ODUj/ODUflex client streaming data (1 >= number of streams <= 96) on a channelized basis
  • XCI4FIC - Complies with Interlaken Protocol Definition Revision 1.2 Specifications
Alliance Member IP Xelic, Inc.

40G/100G Ethernet Mapping: XCO3M, XCO4M, XCRMON

  • Block Alignment, Lane Alignment/Deskew, PCS performance monitoring
  • Ethernet 40GBASE-R signal transcoding
  • Ethernet 100GBASE-R mapping and demapping
  • Provides ability to count all commonly require packet statics
Alliance Member IP Xelic, Inc.

1G/10G Ethernet Mapping: XCO0M, XCE10GA, XCI2PX, XCO2M, XCRMON

  • Frame Mapped/Transparent Mode GFP mapping
  • Provides alignment of incoming data and decodes 10B data into 8B characters
  • Mapping of XGMII signals into 66-bit PCS blocks (and vice-versa) using a 64B/66B coding scheme
  • Provides ability to count all commonly require packet statics.
Alliance Member IP Xelic, Inc.

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Packet-Based Processing Featuring SDNet Specification Environment
Topic Resource Type Provider
Packet-Based Processing Specification Design Environment for Networking (SDNet)
SDNet enables the easy creation of high performance packet processing systems, based on compiling high-level user defined specifications to highly optimized All Programmable FPGAs and SoCs.  This specification allows a user to describe required packet processing functions in a natural way, without including any implementation detail.  This description is then automatically transformed into an optimized hardware implementation on Xilinx All Programmable devices that delivers line rate performance at optimal cost, power and performance.

The main components of the SDNet specification environment are:

  • Generation of custom hardware components for specific functions (e.g., parsing, editing)
  • Generation of custom packet data plane hardware subsystems to meet user requirements
  • Generation of custom firmware for generated SDNet hardware architectures
  • Generation of verification and validation test benches

A summary of the packet processing functions supported by SDNet includes:

  • L2-L7 protocol parsing at 100% line rate for min packet size with in-service parsing depth upgrades
  • Search & classification – up to 64K entries dynamically parameterized with dynamic table management
  • Editing Data Path – swapping protocol header fields at 100% line rate ,
  • Packet processing SmartCOREs also offer hitless in-service upgrade capabilities, reducing CAPEX and OPEX
  • Per-Flow Traffic Management – dynamically parameterized with 5+ levels of hierarchy / QoS per queue, with up to 64K queues supported. Traffic manager is dynamically managed with the suite of unified APIs. 
For further information please contact your local Sales Representative.
SmartCORE IP Xilinx, Inc.
Traffic Management IP Suite
  • Unified architecture scalable across bandwidth 10Gbps to 100Gbps (200 Gbps upcoming) and number of queues from 2K to 64K)
  • Support for min Ethernet packet size (at full line-rate) and jumbo frames.
  • Scalable architecture enabling up to 5+ levels of scheduling hierarchy, where each level could be independently configured with policing, shaping, scheduling and congestion/flow control features
  • Congestion control: TD, RED, and WRED
  • Flow control -per queue/per aggregate of queues/per hierarchy
  • Scheduling: SP, Deficit Weighted Round Robin(DWRR), patent pending SP+ (for optimal combination of scheduling functions)
  • Policing: discard or marking based on srTCM, trTCM, and mefTCM, 
  • All QoS parameters managed dynamically with the set of unified APIs
For further information please contact your local Sales Representative
SmartCORE IP Xilinx, Inc.
  Suite of SmartCore Embedded Parsers
Xilinx offers a wide portfolio of packet parsing SmartCORE IPs able to extract variable data fields from header or payloads at the rate of 150 million packets per second per individual Smart CORE IP. Multiple SmartCORE IPs could be instantiated for even deeper packet content analysis.
  • Handles any packet format
  • Up to 16-deep protocol stacks could be built to address customer’s exact specification
  • Scalable architecture; supports from 1Gb/s to 100Gb/s in Kintex-7, Virtex-7 and Ultrascale devices.
  • Protocol agnostic wire speed guarantee
  • Seamless integration with Xilinx’s LogiCORE IP, connectivity SmartCORE IP, and user IP blocks.
For further information please contact your local Sales Representative.
SmartCORE IP Xilinx, Inc.
  Suite of SmartCORE Embedded Search Engines
Xilinx embedded search portfolio addresses next generation packet processing including route lookup, packet filtering, Quality of Service classification, content matching, load balancing and more.

Exact Match SmartCORE IP, Longest Prefix Match Smart CORE IP, TCAM SmartCORE IPsuites are easily parameterized and deliver the exact customer specification. The portfolio supports flexible data plane processing from 1Gbps to 100Gbps per individual SmartCORE IP instance - with typical rates of up to 200 million searches per second, with a wide range of key and return value sizes, flexible table aging and rapid update rate.

While addressing system needs in lower cost and reduced power, Xilinx embedded search SmartCORE IPs offer high search rate and low latency required by next generation networks.

A collection of application-customized search engines can be combined together to implement a wide range of optimized searches including:
  • Exact match CAM for Ethernet destination address lookup:  64K entries, 48 bits wide
  • Exact match CAM for Ethernet source address learning:  4K entries, 48 bits wide
  • Longest-prefix match for IPv4 destination address lookup:  64K entries, 32 bits wide
  • Longest-prefix match for IPv6 destination address lookup: 8K entries, 128 bits wide
  • Ternary CAM for ACL lookup: 4K entries, 112 bits wide

For further information please contact your local Sales Representative.

SmartCORE IP Xilinx, Inc.
 
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