Wireless IP, Reference Designs and Documentation

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Baseband Processing
RF (Radio Card)
Interfaces and Connectivity

Baseband Processing
Topic	Resource	Type	Provider
LTE	LTE Baseband Uplink Targeted Reference Design v2.0 3GPP-LTE (v9.0) PUSCH eNB receiver 10MHz bandwidth, FDD frame structure Support for 2 antennas, including 2 user MU-MIMO Targets Virtex®-6 (ML605 development board) EDK project Requires the following LogiCORE™ IP: v2.0 LTE Channel Decoder, v2.0 LTE Turbo Decoder, v7.0 FFT, v3.1 DFT, v1.0 LTE MIMO Decoder Documented in XAPP1072	Reference design	Xilinx, Inc.
	LTE Baseband Downlink Targeted Reference Design v2.0 EDK project 3GPP-LTE (v9.0) eNB transmitter 10MHz bandwidth, FDD, normal cyclic prefix 2 antenna transmit diversity Targets V6LX240T LogiCORE IP required: v2.1 LTE Channel Encoder, v3.1 LTE Turbo Encoder, v7.0 FFT, v2.0 LTE MIMO Encoder Documented in xapp1115	Reference design	Xilinx, Inc.
	LTE Baseband Targeted Design Platform System Reference Design v2.3 Integrates v2.0 LTE Baseband Uplink and Downlink Targeted Reference Designs Includes CPRI LogiCORE for industry standard connectivity to digital front end MicroBlaze™ processor provides system control and Layer1/Layer2 API Uplink and Downlink HARQ transmissions supported Targeted to Virtex-6 evaluation board (ML605) + XM104 Connectivity FMC Documented in XAPP1120	Reference design	Xilinx, Inc.


	Discrete Fourier Transform	LogiCORE IP	Xilinx, Inc.
	3GPP LTE Channel Decoder	LogiCORE IP	Xilinx, Inc.
	3GPP LTE Channel Encoder	LogiCORE IP	Xilinx, Inc.
	3GPP LTE Channel Estimator	LogiCORE IP	Xilinx, Inc.
	3GPP LTE Fast Fourier Transform	LogiCORE IP	Xilinx, Inc.
	3GPP LTE MIMO Decoder	LogiCORE IP	Xilinx, Inc.
	3GPP LTE MIMO Encoder	LogiCORE IP	Xilinx, Inc.
	3GPP LTE PUCCH Receiver	LogiCORE IP	Xilinx, Inc.
	3GPP LTE RACH Detector	LogiCORE IP	Xilinx, Inc.
	3GPP LTE Turbo Decoder	LogiCORE IP	Xilinx, Inc.
	3GPP LTE Turbo Encoder	LogiCORE IP	Xilinx, Inc.
	3GPP Mixed Mode Turbo Decoder	LogiCORE IP	Xilinx, Inc.
WCDMA/HSPA
	RACH Preamble Detector	LogiCORE IP	Xilinx, Inc.
	Searcher	LogiCORE IP	Xilinx, Inc.
	TCC Encoder	LogiCORE IP	Xilinx, Inc.
	TCC Decoder	LogiCORE IP	Xilinx, Inc.
WiMAX
	CTC Encoder	LogiCORE IP	Xilinx, Inc.
	CTC Decoder	LogiCORE IP	Xilinx, Inc.

Building Blocks	Discrete Fourier Transform (DFT)	LogiCORE IP	Xilinx, Inc.
	Fast Fourier Transform (FFT)	LogiCORE IP	Xilinx, Inc.
	Reed-Solomon IP	Custom search	Xilinx, Inc.
	Viterbi/Convolutional IP	Custom search	Xilinx, Inc.

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RF (Radio Card)
Topic	Resource	Type	Provider
DUC/DDC Compiler	DUC/DDC Compiler Device Architecture: Artix™-7, Kintex™-7, Virtex-7, Zynq™-7000 and Virtex-6 Supports LTE, TD-SCDMA and WCDMA LTE support for 1.4, 3, 5, 10, 15, 20MHz. TD-SCDMA and WCDMA Supports up to 30 carriers per antenna path (depending on carrier bandwidth and air interface standard) Supports multiple antennas Supports DUC output sample rates ranging from 30.72MSPS to 245.76MSPS Supports DDC input sample rates ranging from 30.72MSPS to 184.32MSPS Programmable carrier spacing and position Supports Fs/4 down conversion in DDC Implementation options to configure clock rates, enable optional control signals and specify resource usage statistics Data interfaces support for AXI4-Streaming Interface compliant with AMBA 3 APB Specification C Model simulation support	LogiCORE IP	Xilinx, Inc.
Peak Cancellation Crest Factor Reduction (PC-CFR)	Peak Cancellation Crest Factor Reduction Device architecture: Artix-7, Kintex-7, Virtex-7, Virtex-6, Virtex-5, and Spartan-6 Supports WCDMA, TD-SCDMA, WiMAX, LTE, GSM and CDMA2000 Parameterizable selection of clocks/output sample from 1 to 8 to enable optimum area to be achieved with various output sample rates Parameterizable selection of Cancellation Pulse Generators (CPG's) from 1 to 8 to allow optimum performance vs area trade off Parameterizable selection of number of antennas from 1 to 8 Single netlist supporting multiple iterations from multiple antennas to reduce overall implementation complexity and improve ease of use Increased length of Cancellation Pulse to 2048 to support air interfaces up to 100MHz Latency control to allow low latency implementations (Repeater applications) Matlab simulator for creation of waveform-specific pulse coefficients and automatic generation of Coregen .coe coefficient file C Model simulation support	LogiCORE IP	Xilinx, Inc.
Digital Pre-Distortion (DPD)	Digital Pre-Distortion IP Core Device support: Artix-7, Kintex-7, Virtex-7, Zynq 7000, Virtex-6 Support for variable clocks per output sample (1 -4) to allow DPD expansion bandwidth tradeoff over implementation area Support for 1, 2, 4, 8 Transmit Antennas, with a shared update engine Supports 1Fs, 2Fs Real or Complex IF feedback path Support for FIFO ADC interface (burst mode ADC devices) Supports variable memory matrix parameterization allowing area/cost vs. correction performance tradeoff Optional support for hardware accelerated signal alignment to reduce convergence time Optional support for hardware accelerated Least Squares processing to reduce convergence time Optional Tx QMC Optional Rx QMC Advanced debug interface ACLR correction up to 33dB Support for up to 80MHz of transmit BW	LogiCORE IP	Xilinx, Inc.
Envelope Tracking (ET)	Envelope Generation Interface Open ET-compatible digital interface to Envelope Tracking modulators Up to 125 Msps sampling frequency, typically 122.88 Msps for W-DCMA/LTE 16-bit I/Q input / 14-bit LVDS envelope output Programmable envelope gain for matching RF gain / envelope Data bypass feature for test and evaluation purposes Programmable sub-sample and whole sample delay blocks for RF signal alignment Programmable dual-page Envelope Shaping look-up table Tested with Xilinx CFR and DPD cores	3rd Party Reference Design	Nujira Ltd.
WiMAX	WiMAX Reference Design (login required) Device architecture: Virtex-4, Virtex-5 FPGA DUC: 1 carrier (dynamic switching 3.5, 5, 7, and 10 MHz) DDC: 1 carrier (dynamic switching 3.5, 5, 7, and 10 MHz) CFR: 1 carrier (PAPR>1.5 dB@2% EVM)	Reference design	Xilinx, Inc.
WiMAX	WiMAX Reference Design (login required) Device architecture: Spartan-3A DSP FPGA DUC: 1 carrier (dynamic switching 5 and 10 MHz) DDC: 1 carrier (dynamic switching 5 and 10 MHz)	Reference design	Xilinx, Inc.
DUC/DDC	Modulation and demodulation IP Device architecture: various	Custom search	Xilinx, Inc. and partners
	XAPP1018 - Designing Efficient DUC/DDC with System Generator and Core Generator (PDF)	App note	Xilinx, Inc.
	Design Files: xapp1018 cdma2000.zip	Zip file	Xilinx, Inc
	Design Files: xapp1018 wcdma.zip	Zip file	Xilinx, Inc
	XAPP1113 - Designing Efficient Digital Up and Down Converters for Narrowband Systems (inc. Multi-Carrier GSM example) (PDF) Device Architecture: Virtex-5 DUC and DDC for 4-carrier GSM	App note	Xilinx, Inc.
	Design Files: xapp1113.zip	Zip file	Xilinx, Inc.
Building Blocks	FIR Compiler	LogiCORE IP	Xilinx, Inc.
Building Blocks	CIC Compiler	LogiCORE IP	Xilinx, Inc.

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Interfaces and Connectivity
Topic	Resource	Type	Provider
OBSAI	OBSAI IP Core	LogiCORE IP	Xilinx, Inc.
CPRI™	CPRI IP Core	LogiCORE IP	Xilinx, Inc.
CPRI Multi-hop	CPRI Multi-hop Remote Radio Head Reference Design	App note	Xilinx, Inc.
JESD204	JESD204 IP Core	LogiCORE IP	Xilinx, Inc.
JEDEC JESD204A	JEDEC JESD204A FPGA Receive Reference Design	LogiCORE IP	Xilinx, Inc.
SRIO Gen 2	Serial RapidIO Gen 2	LogiCORE IP	Xilinx, Inc.
SRIO Gen 1.3	Serial RapidIO Gen 1.3	LogiCORE IP	Xilinx, Inc.
PCI Express®	Development Kit for PCI Express	Development kit	Xilinx, Inc.
Ethernet MAC	Ethernet MAC built-in hard IP for Virtex-6 FPGA	Silicon feature	Xilinx, Inc.
EMIF	XAPP753 - FPGA Interface to the TMSC6000 DSP Platform Using EMIF (PDF)	App note	Xilinx, Inc.
High Speed ADC/DAC Interface	ADC/DAC application notes	App note	Xilinx, Inc.

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