Wireless IP, Reference Designs and Documentation

Backhaul
Topic Resource Type Provider
Modems Gigabit class Point to Point 1024QAM Microwave Modem

  • Data rate up to 1Gbps
  • Modulation: QPSK to 1024QAM
  • Symbol rate: software configurable 2-100
  • Adaptive Modulation with software defined profile
  • Closed loop adaptive Digital Pre-Distortion
  • Reed-Solomon FEC with configurable code rate
  • Graphical User Interface
SmartCORE Xilinx, Inc.
256QAM Millimeter Wave Modem (vBand / eBand)

  • Data rate up to 1Gbps
  • TDD of FDD
  • Modulation: QPSK to 256QAM
  • Symbol rate: software configurable up to 223MSym/s (optionally up to 446MSym/s)
  • Adaptive Modulation with software defined profile
  • Closed loop adaptive Digital Pre-Distortion
  • Reed-Solomon FEC or LDPC FEC with configurable code rate
  • Graphical User Interface
SmartCORE Xilinx, Inc.
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Baseband Processing
Topic Resource Type Provider
LTE

LTE Baseband Targeted Design Platform System Reference Design

  • Downlink targeted for a Kintex-7, Virtex-7, or Zynq-7000 platform, demonstrating the implementation of a comprehensive downlink transmit design based on Release 10 of the LTE specifications
Reference design Xilinx, Inc.

Discrete Fourier Transform

  • Support for Direct and inverse DFT on a frame-by-frame basis
  • Support for a wide range of transform sizes
LogiCORE IP Xilinx, Inc.

3GPP LTE Channel Decoder

  • Implementation of UL-SCH channel decode functions
  • Support for HARQ combining
  • Support for FDD and TDD
SmartCORE IP Xilinx, Inc.

3GPP LTE Channel Encoder

  • Support for PDSCH, PMCH, PPCH, PDCCH and PBCH channel types
  • Inclusion of Turbo Encoder
  • Support for FDD and TDD
  • Scalable from high throughput multiple codeword eNodeBs to Femtocells
LogiCORE IP Xilinx, Inc.

3GPP LTE Channel Estimator

  • Support of channel estimation for PUSCH channel
  • Support for SISO, SIMO, and MU-MIMO antenna configurations
SmartCORE IP Xilinx, Inc.

3GPP LTE Fast Fourier Transform

  • Support for all point sizes (128, 256, 512, 1024, 1536, 2048)
  • Optional support for run-time configurable point size
LogiCORE IP Xilinx, Inc.

3GPP LTE MIMO Decoder

  • Implementation of a highly resource optimized and scalable MIMO decode function
  • Support for up to 4x4 antenna configurations
  • Support for up to 20 MHz
  • Support for FDD and TDD
SmartCORE IP Xilinx, Inc.

3GPP LTE MIMO Encoder

  • Implementation of layer mapping and pre-coding
  • Support for both transmit diversity and space division multiplexing schemes
  • Optional support for cyclic delay diversity
  • Maximum theoretical throughput supported for systems with up to 20 MHz bandwidth
SmartCORE IP Xilinx, Inc.

3GPP LTE PUCCH Receiver

  • Implementation of complete receive functionality for PUCCH
  • Support for all control formats (1, 1a, 1b, 2, 2a and 2b)
  • Support for mixed format
  • Support for normal and shortened slots
  • Support for normal and extended cyclic prefix
SmartCORE IP Xilinx, Inc.

3GPP LTE RACH Detector

  • Implementation of a highly resource optimized and scalable RACH decode function
  • Support for all 5 RACH formats
  • Support for up to 64 Zadoff-Chu root sequences
  • Support for up to 4 antennas
  • Support for up to 20MHz
  • Support for FDD and TDD
SmartCORE IP Xilinx, Inc.

3GPP LTE Turbo Decoder
Please note that this core has been discontinued and replaced by 3GPP Mixed Mode Turbo Decoder core.

SmartCORE IP Xilinx, Inc.

3GPP LTE Turbo Encoder

  • Implementation of turbo convolutional encoding scheme
  • Inclusion of interleaver function
SmartCORE IP Xilinx, Inc.

3GPP Mixed Mode Turbo Decoder

  • Implementation of a flexible turbo convolutional decode function for both LTE and UMTS air interfaces
  • Scalable and optimized for all basestation form factors, from femtocell to macrocell
  • Support for LTE only, UMTS only, or both
  • Dynamic decoding of LTE and UMTS data on a block by block basis
  • Configurable with either 1, 2, 4 or 8 decode units, allowing resource optimization based on system needs
SmartCORE IP Xilinx, Inc.
WCDMA/HSPA

TCC Encoder

  • Implementation of turbo convolutional encoding scheme
  • Inclusion of interleaver function
  • Support for full 3GPP block size range: 40 - 5114
  • Support for up to 16 simultaneous data channels
  • Support for double-buffered symbol memory for maximum throughput
  • Support for internal or external interleaver allowing the use of custom interleavers
  • Support for rate 1/3 and also rate 1/5 for additional error correction capability
SmartCORE IP Xilinx, Inc.

TCC Decoder

  • Implementation of turbo convolutional decode function
  • Inclusion of interleaver function
  • Support for full 3GPP block size range: 40-5114
  • Support for rate 1/3 or rate 1/5 coded input
SmartCORE IP Xilinx, Inc.
WiMAX

CTC Encoder

  • Implementation of convolutional turbo encoding scheme
  • Compliant with IEEE Std 802.16e-2005 and IEEE Std 802.16-2004/Cor1-2005
  • Support for all modulation schemes including 64-QAM mode
  • Support for HARQ for all block sizes
  • Supoprt for simultaneous C1 and C2 encoding plus triple buffered memory delivering high throughput
SmartCORE IP Xilinx, Inc.

CTC Decoder

  • Implementation of convolutional turbo decode function
  • Support for all interleaver block sizes including HARQ mode: 24, 36, 48, 72,96, 108, 120, 144, 180, 192, 216, 240, 480, 960, 1440, 1920 and 2400 pairs
  • Support for dynamic block size switching without interruption
  • Support for programmable number of iterations dynamically changeable per block
  • Support for parameterizable options for soft data input, extrinsic bits, and accumulated state metric
  • Support for adaptive rate change via puncturing interface
  • Support for parallel processing with parameterizable number of SISOs (1 to 8) to achieve high throughput
SmartCORE IP Xilinx, Inc.
1588v2 Timing Synchronization

IPC1703

  • Standalone IEEE1588v2 standard compliant Master/Slave Ordinary Clock chip on FPGA
  • Hybrid 1588/Sync mode support
  • Meets UMTS, GSM/GPRS/EDGE, TD-SCDMA, WiMAX and LTE frequency and ToD accuracy requirements
  • ToD accuracy better than ±1µsec under ITU-T G.8261 conditions
  • Fractional frequency offset (FFOFF) performance better than 16ppb under ITU-T G.8261 conditions
Alliance Member IP IPClock Ltd.
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Interfaces and Connectivity
Topic Resource Type Provider
OBSAI

OBSAI IP Core

  • Designed to OBSAI RP3 Specification v4.2 for up to 6G line rates
  • Operates at line rates of 768, 1536, 3072 and 6144 Mbps 
  • Implements Physical and data link layer functions
  • Includes RP3-01 Auto-negotiation
  • Configurable as master or slave
  • Provides RP1 Ethernet Messages
  • Supports Generic Message Interface for Generic Packets
  • Microprocessor neutral configuration interface
LogiCORE IP Xilinx, Inc.
CPRI™

CPRI IP Core

  • Designed to CPRI Specification v6.0
  • Operates at line rates of 614.4 Mbps, 1228.8 Mbps, 2457.6 Mbps, 3072, 4915.2, 6144, 9830.4 Mbps, 10137.6 Mbps 
  • Automatic speed negotiation
  • Configurable as master or slave
  • Suitable for use in both Radio Equipment Controllers (RECs) and Radio Equipment (RE), including multi-hop systems / daisy chained
LogiCORE IP Xilinx, Inc.
CPRI Multi-hop CPRI Multi-hop Remote Radio Head Reference Design App note Xilinx, Inc.
JESD204

JESD204 IP Core

  • Designed to JEDEC JESD204B specification
  • Supports 1, 2, 3, 4, 5, 6, 7, and 8 lane configurations
  • Supports scrambling and initial lane alignment
  • Supports 1-256 Octets per frame and 1-32 frames per multi-frame
  • Provides Physical and Data link layer functions
  • AXI4-Stream interface for data
AXI4-Lite for configuration interface
LogiCORE IP Xilinx, Inc.
JEDEC JESD204A JEDEC JESD204A FPGA Receive Reference Design LogiCORE IP Xilinx, Inc.
SRIO Gen 2

Serial RapidIO Gen 2

  • 1x, 2x, & 4x Serial PHY - Supports Kintex-7, Virtex-7, and Virtex-6 FPGAs
  • 1x, 2x & 4x Serial PHY - Supports 1.25, 2.5, 3.125, 5.0, and 6.25 Gpbs line speed
  • Supports IDLE1 and IDLE2 sequence
  • Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
  • Support for 8/16 bit device IDs, programmable source ID on all outgoing packets
  • Support for priority based re-transmit suppression
  • Independently configurable 8/16/32 packet deep TX and RX buffer depths
  • AXI4-Stream interface for Data path and AXI4-Lite for the configuration Interface
LogiCORE IP Xilinx, Inc.
PCI Express® Development Kit for PCI Express Development kit Xilinx, Inc.
Ethernet MAC Ethernet MAC built-in hard IP for Virtex-6 FPGA Silicon feature Xilinx, Inc.
EMIF XAPP753 - FPGA Interface to the TMSC6000 DSP Platform Using EMIF (PDF) App note Xilinx, Inc.
High Speed ADC/DAC Interface ADC/DAC application notes App note Xilinx, Inc.
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RF (Radio Card)
Topic Resource Type Provider
Digital Up Conversion/ Digital  Down Conversion (DUC/DDC)

DUC/DDC Compiler

  • Supports LTE, TD-SCDMA and WCDMA
  • 1-30 carriers per antenna (bandwidth dependent)
  • 1-8 antennas
SmartCORE IP Xilinx, Inc.
Modulation and demodulation IP
Device architecture: various
Custom search Xilinx, Inc. and partners
XAPP1018 - Designing Efficient DUC/DDC with System Generator and Core Generator (PDF) App note Xilinx, Inc.
Design Files: xapp1018 cdma2000.zip Zip file Xilinx, Inc.
Design Files: xapp1018 wcdma.zip Zip file Xilinx, Inc.
XAPP1113 - Designing Efficient Digital Up and Down Converters for Narrowband Systems (inc. Multi-Carrier GSM example) (PDF)
Device Architecture: Virtex-5 DUC and DDC for 4-carrier GSM
App note Xilinx, Inc.
Design Files: xapp1113.zip Zip file Xilinx, Inc.

Crest Factor Reduction (CFR)

Peak Cancellation Crest Factor Reduction

  • Supports LTE, TD-SCDMA, WCDMA, CDMA2000, WiMAX and GSM (including frequency hopping MC-GSM)
  • Support for Multi-RAT capability with maximum bandwidth support up to 100MHz in Single RAT and up to 80MHz in Multi-RAT configurations
  • 1-8 antennas
  • Parameterizable iteration engines
SmartCORE IP Xilinx, Inc.

Digital Pre-Distortion (DPD)

Digital Pre-Distortion IP Core

  • Supports LTE, WCDMA, TD-SCDMA, CDMA2000, WiMAX, and MC-GSM with frequency hopping
  • Support for multi-RAT configurations
  • Support for up to 100MHz signal bandwidth
  • Up to 40dB ACLR correction
  • 1-8 antennas
SmartCORE IP Xilinx, Inc.
Building Blocks FIR Compiler LogiCORE IP Xilinx, Inc.
CIC Compiler LogiCORE IP Xilinx, Inc.
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