Events
| Join us at DesignConŽ 2010 by Xilinx booth #521 to learn about our comprehensive connectivity platforms that enable design flexibility, innovation and fast time-to-market. | |
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| Demonstrations on display will include Virtex®-6 HXT FPGAs, Virtex-6 and Spartan®-6 Connectivity Kits as well as SiSoft IBIS-AMI Simulation Models. | |
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Learn more about Xilinx Connectivity Platform Solutions. |
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About DesignCon 2010 For more than a decade, DesignCon has delivered quality conference programming complemented by an innovative technology exhibition representing all sectors of the electronic-design and semiconductor industries. DesignCon 2010 is no exception and promises to be the very best yet with the inclusion of the all-new PCB Summit as well as the IP Summit, now in its second year! DesignCon is the definitive event for electronic design experts spanning chip, package, board, and system domains, addressing common issues in signal integrity, power management, interconnection, and design verification.
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Events by Region
North America Event Schedule
EMEA Event Schedule
Events by Date
Event:Cadence AllegroŽ and OrCADŽ 16.3 Virtual Conference
Date:Available on Demand
Location:Your Desktop
Thanks For Visiting Xilinx At This Event
Thanks For Visiting Xilinx At This Event
X-fest Global Events
October 2009 - February 2010
X-fest is a global series of FREE technical seminars sponsored by Avnet and Xilinx offering practical training for engineers.To date, nearly 4,200 people have registered to attend X-fest worldwide. These one-day seminars offer several 75-minute training courses for attendees to choose from, designed to provide specialized training on design solutions for FPGA circuitry and the components surrounding FPGAs.
Attendees also have access to design solutions from sponsors including Cypress Semiconductor, Emerson Network Power, Intel, Maxim Integrated Products, Molex, National Semiconductor, Numonyx, NXP Semiconductors, Texas Instruments (TI), and Tyco Electronics. Xilinx will showcase multiple demonstrations and development platforms, including interfacing DDR3 and LPDRAM with the Xilinx SpartanŽ-6 hard memory controller, interfacing to an analog world, and designing products for the human experience.
X-fest Global Schedule
Cadence AllegroŽ and OrCADŽ 16.3 Virtual Conference
Register to join us for this exclusive virtual event. You'll participate in a content-rich day-long program that will include the latest Cadence PCB and IC packaging/SiP design technology from our 16.3 release, plus you'll hear from our strategic partners and industry experts.
Date:December 2, 2009
Location:Your Desktop
Featured Demonstration from Brian Jackson, Director of Software Development, Xilinx:
Using Cadence FPGA System Planner and Xilinx PlanAhead™ technology to optimize FGPA on PCB performance
The demonstration will describe the advantages of using the Cadence FPGA System Planner coupled with Xilinx's PlanAhead tool to optimize the interconnect and I/O pin definitions for the various FGPAs on the PCB. The System Planner is used to first define the FPGA on PCB interface signals and then to synthesize the optimal I/O pinout to reduce PCB routing congestion. The initial pinout can then be passed to the Xilinx FPGA design tools to validate and improve upon based on internal FPGA resource and interconnect requirements. The System Planner solution will demonstrate how I/O pinout modifications can then easily be passed back and forth between PCB and FPGA designers.
System-on-Chip Virtual Conference
Join Xilinx at this EETimes virtual conference that explores the challenges faced by developers of ASIC- and FPGA-based SoC designs. Learn how Xilinx Targeted Design Platforms give you the agility to adapt quickly and the freedom to innovate your next SoC design.
Date:Available on Demand
Location:Your Desktop
Attend panel discussions and Xilinx exclusive presentations
The Economics of Next Generation SoC Design: A Node too far?
featuring panelist Steve Douglass, Vice President Product Development
Intellectual Property: Is the Dream of Plug and Play Dead?
featuring panelist Tom Feist, Senior Director, ISE Design Suite
Addressing the Performance Bottleneck in Modern SOC Design
presented by Panch Chandrasekaran, Senior Manager, High-Speed Serial I/O
The conference is a completely virtual experience. The fully interactive environment enables you to chat with experts, visit exhibit booths, view speaker sessions, sign up for give-aways and more. Because the conference is online you never have to leave the office.