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High Performance System Design Seminars: Dayton, OH

Date: April 28, 2009
Location :
Holiday Inn I-675 - Fairborn
2800 Presidential Dr.
Fairborn, OH 45324
937-426-7800
http://www.holiday-inn.com/fairbornoh

Register Now!

  Time   Topic
8:30am - 9:00am
Registration & Breakfast
9:00am - 10:00am Programmable Solutions for Today and Tomorrow's Design Challenges
10:00am - 10:45am Next Gen. ISE Design Suite 11.1
10:45am - 11:00pm
Break
11:00pm - 12:00pm
Connectivity Track Processing Track
Designing with high-speed serial transceivers in FPGAs (3G and 6.5G)
Embedded processing in FPGAs - Hardware (PowerPC 440 or MicroBlaze based on region)
12:00pm - 1:00pm
Lunch and Exhibits
1:00pm - 2:00pm
Modeling and debugging a serial link
Embedded processing in FPGAs - Software
(Linux, RTOS)
2:00pm - 2:15pm
Break
2:15pm - 3:15pm
Implement PCI Express (gen 1 & gen 2) in FPGAs
DSP design using System Generator
3:15pm - 4:15pm
Designing memory interfaces with FPGAs
FPGA system design with built-in processor and DSP blocks (Video example)
4:15pm - 4:30pm
Wrap-up and Prizes

General Session Abstract
Programmable Solutions for Today and Tomorrow's Design Challenges - An overview of the Xilinx current and next generation products and solution, both in terms of key features, platforms and applications they enable.

Connectivity Track Abstracts
Building Robust Serial Links for 3G and 6.5G Applications - This presentation provides an introduction to serial transceivers in Virtex FPGAs, GTP/GTX, supported protocols, char reports, and boards along with a design checklist. Attendees will learn about serial link analysis and Do's and Donts in link debug for various use cases (chip-chip, backplanes, etc).

Implement PCI Express (Generation 1 & 2) in FPGAs - This presentation covers PCI Express protocols (gen 1 and gen2), their key concepts and interoperability. Attendees can learn how to create a PCIe design using Xilinx IP tools and see a demo for PCIe gen 2. Example applications and use models with multiple end points are presented.

Designing Memory Interfaces with FPGAs - Learn about Xilinx tools and solutions for memory interface and controller design. Learn about the design techniques used to implement high performance memory interfaces and how to use the Memory Interface Generator (MIG) tool to generate your own customized design including RTL and ucf files. Development boards are used to see a memory interface design and verify operation with Chipscope™ Pro.

Processing Track Abstracts
Embedded Processing in FPGAs for Hardware Engineers - An overview of Xilinx MicroBlaze™ and PowerPC™ processors showing how to create a embedded processing application in FPGAs. Attendees will learn about the tool flow (EDK), and implementing an example design.

Embedded Processing in FPGAs for Software Engineers (Linux, RTOS) - Designed for software engineers, this presentation will delve into FPGA-based embedded processing software. Attendees will learn about Linux and RTOS from 3rd parties along with tools from Xilinx.

DSP Design in FPGAs Using System Generator - Digital signal processing in FPGAs is becoming increasingly popular due to the rich parallelism that FPGAs offer for multi-channel applications in communications and real-time multimedia applications. Attendees will learn about using Xilinx System Generator and link to Mathworks' MATLAB tools to develop DSP designs easily.

FPGA System Design with Built-in Processor and DSP Blocks (Video Example) - In this presentation, attendees will learn about full SoC design with an embedded processor, DSP engines and FPGA logic all connected to an on-chip bus. While the concepts are applicable to multiple applications, an example design focused on video applications is shown.



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