Webcasts

 

 

Design Tools
Title Description Recording Info.

Vivado In-System Debug

 

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado® Design Suite. Duration: 15 mins
Static Timing Analysis and Constraint Validation Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado® Design Suite. Duration: 15 mins
Vivado Design Suite - Integrated Design Environment Software engineers have long depended on integrated design environments (IDEs) to help manage complex design processes. Now, hardware engineers can take advantage of the same complexity-taming level of integration. In this episode of Chalk Talk, Amelia Dalton explores the IDE in Vivado® Design Suite with Brian Lay of Xilinx. Duration: 17 mins
Vivado IP Integrator Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado® Design Suite. Duration: 9 mins

Scripted Flows in Vivado Design Suite

 

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado® Design Suite. Duration: 16 mins
Vivado IP Flows Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado® Design Suite. Duration: 10 mins

How to Accelerate OpenCV Applications with Zynq-7000 All Programmable SoC using Vivado HLS Video Libraries

 

In this presentation, you will learn how to rapidly accelerate real-time computer vision algorithms and integrate them into your designs using Xilinx Zynq®7000 All Programmable SoC devices. Step-by-step examples will show you how to build and integrate custom video accelerators by migrating functions from the OpenCV library or your own custom video algorithms into your embedded design using guaranteed-to-synthesize HLS (High-level Synthesis) video libraries; the Vivado® HLS compiler; and the Vivado IP Integrator. This design flow allows you to implement real-time embedded computer-vision algorithms using a seamless combination of high-performance, low-power, on-chip programmable hardware for high-data-rate (full HD) pixel-processing tasks and software-programmable ARM processor cores for frame-based processing tasks that operate at lower data rates. Duration: 60 mins
Applications
Title Description Recording Info.
Designing Cost-effective, Greener LTE Basestations with Xilinx FPGAs Exponential growth in mobile data has fuelled enormous interest in 4G wireless technology such as LTE. However, the increased processing constraints placed provide a significant challenge in meeting the dual imperatives of base station cost and power reduction. This webcast will describe how Xilinx FPGAs and IP help resolve these issues, providing a scalable and reconfigurable platform for base station development. Duration: 60 mins
Connectivity
Title Description Recording Info.
Building Optically Compliant High Performance Serial Links at 10G, 100G and 400G In order to meet increasing bandwidth demands, communication equipment vendors are building 40G, 100G and looking toward to the next generation 400G systems with as few changes to the existing infrastructure as possible. They demand more of the Programmable Platforms and semiconductor chips that interface with the optical modules both in terms of functionality as well as performance to double bandwidth capacity, to maintain power density and to lower costs. This webcast elaborates on the design requirements—architecture, circuit techniques, and system level considerations—to build optically compliant serial interfaces for the 40G/100G and 400G systems. Duration: 60 mins
Accelerating High-Bandwidth System Design Implementations with FPGA-based platforms Attend this webcast and learn how the Targeted Reference Design, delivered through the Xilinx Connectivity Kits, jumpstarts application development by providing a complete design flow for a end-to-end system application hardware design and RTL source files, simulation environment, implementation flows and scripts, software device driver source files, performance / status monitor application and documentation Duration: 60 mins
Smarter Vision
Title Description Recording Info.
Seeing is Believing: Develop High-Performance Machine Vision Systems Faster than the Blink of an Eye In this webinar, Xilinx and Silicon Software explore an embedded machine vision design approach that addresses the many challenges and the performance requirements of 21st-century machine vision. This webinar will provide concrete benchmark data that sharply contrasts the performance of a pure software implementation versus one that’s been accelerated with hardware. The webinar will also introduce easy-to-use tools that can help you design and deploy a hardware/software system that meets all of your machine vision system requirements. Duration: 60 mins
How to Drive Multiple Live Cameras and Displays for Pennies The MIPI Display Serial Interface (DSI) and Camera Serial Interface 2 (CSI-2) are becoming key, low-cost industry standards for connecting video displays and cameras to a wide variety of embedded systems. You can now incorporate these MIPI interfaces into FPGA-based systems. Want to know more? Xilinx and its Alliance members Xylon and Northwest Logic present a webinar to help you design MIPI’s DSI and CSI-2 interfaces into your next system at a surprisingly low cost. If your system must fuse video streams from multiple cameras or if you need to drive multiple displays—even 4K cameras and displays—then this webinar is especially for you. Working with video in automotive systems? You will also want to see this webinar because of the low-cost aspects of the MIPI video interfaces. Duration: 60 mins
Designing Advanced Embedded Systems with Xilinx Zynq All Programmable SoCs This webinar will cover the current landscape for embedded design alternatives: embedded processors, ASSPs, SoCs, and All Programmable SoCs, the types of systems that particularly benefit from the combined processing and I/O capabilities of Zynq® All Programmable SoCs, and how the Xilinx Zynq-7000 All Programmable SoC and the Vivado® Design Suite permit the rapid and efficient development of sophisticated, single-chip hardware/software systems. Duration: 60 mins
Designing Advanced Embedded Systems with Xilinx Zynq: How to Break Software Bottlenecks with Accelerators This webinar will show you how to analyze a design and determine the software that would benefit from acceleration, how to develop and integrate a hardware accelerator and an overview of the Vivado® Design Suite showing the complete, step-by-step way to develop products using the Zynq® platform. Duration: 60 mins
How to Accelerate OpenCV Applications with Zynq-7000 All Programmable SoC using Vivado HLS Video Libraries In this presentation, you will learn how to rapidly accelerate real-time computer vision algorithms and integrate them into your designs using Xilinx Zynq®7000 All Programmable SoC devices. Step-by-step examples will show you how to build and integrate custom video accelerators by migrating functions from the OpenCV library or your own custom video algorithms into your embedded design using guaranteed-to-synthesize HLS (High-level Synthesis) video libraries; the Vivado® HLS compiler; and the Vivado IP Integrator. Duration: 60 mins
Designing Multi-Channel, Real-Time Video Processors with the Xilinx Zynq All Programmable SoC This webinar demonstrates and explores a new Real Time Video Engine (RTVE 2.1) reference design based on the OmniTek OSVP core and running on a Xilinx Zynq®-7000 All Programmable SoC. The RTVE 2.1 reference design accepts 2, 4, or 6 video input channels over SDI or HDMI, processes and combines these streams in real time while performing any necessary format conversions, adds software-generated overlays through alpha blending, and outputs the resulting combined live multi-view video stream on either SDI or HDMI. Duration: 60 mins
Smarter Networks
Title Description Recording Info.
Cloud RAN: The Impact of Base Station Virtualization on Low-latency, High-bandwidth Fronthauling Wireless network architectures are evolving to address an explosive growth in data services. Forecasts predict this will continue for many years and there is a pressing need to supplement traditional Macro cell networks with infrastructure that adds capacity while minimizing capital and operating costs. Two seemingly divergent approaches have emerged to meet this goal. The first is to distribute the baseband processing through an underlay of small cells to co-exist with the Macro cell. This adds capacity but brings challenges around interference management and backhaul complexity. The second is to centralize the baseband processing in a pool of common virtualized resource that can be shared between many tens or hundreds of Remote Radio Heads (RRH). A centralized baseband pool meets the goal of lower operating costs, but comes with a set of challenges around low latency front haul connectivity and switching, between the distributed RRH’s and centralized baseband. This webinar highlights the drivers, benefits and challenges of Cloud RAN, focusing specifically on the complex wired and wireless front hauling mechanisms that can be deployed to make these emerging systems a reality. Duration: 60 mins
Reduce the Power Consumption, Size, and Manufacturing Cost of 4G and 5G Base Stations with FPGA Technology 4G and 5G Heterogeneous Networks (HetNets) must provide increased capacity and throughput with improved coverage while lowering total system cost. The associated base stations will be required to flexibly support wider bandwidths, more antennas, more carriers, and flexible multi-RAT capabilities (multi-carrier GSM, WCDMA, FDD-LTE and TDD-LTE) in a staggering number of configurations to meet all carrier requirements. FPGA technology can instill that flexibility in new base station designs using only a single semiconductor device. You can use programmable-hardware technology to implement complete transmit chains including digital up conversion, crest factor reduction, and digital pre-distortion to improve power amplifier efficiency and complete receive chains that include digital down conversion and interfaces to connect with analog front ends and radio equipment controllers. Don’t miss this free tutorial presentation to see how you can efficiently develop base-station radios using Xilinx All Programmable FPGA technology, which offers significant performance, power, programmability, integration, and price benefits. Duration: 49 mins
Expanding Programmability From the Control to the Data Plane with Xilinx Software Defined Specification Environment The networking industry is moving from the “fixed-function era” where services are built upon proprietary hardware architectures and custom software to the “virtualized-function era” using standard hardware and software-defined networking (SDN). While networking software architectures are evolving rapidly, data-plane hardware often remains bogged down and cannot easily accommodate agile SDN software models. To address this mismatch between SDN software and old-style hardware, Xilinx has introduced the revolutionary ‘softly’ defined network approach which creates a software-defined data plane with content intelligence so that equipment design teams can precisely tailor network hardware that delivers the flexible network services and applications required. This webinar explores open hardware trends in the global market and how network architects can leverage the Xilinx Software Defined Specification Environment for Networking (SDNet) and their revolutionary ‘softly’ defined network approach. Duration: 60 mins
Smarter Connected Control
Title Description Recording Info.
Click and Drag Your Embedded Industrial Controller’s Human Machine Interface Into the 21st Century This webinar will center on the use of ARM-based Xilinx Zynq® All Programmable SoCs for embedded industrial controller design and the ability of Zynq AP SoCs to support smoothly performing graphical HMIs with no need for incremental electronic hardware. This webinar will also include a discussion of reference designs, evaluation kits, and relevant IP and software libraries from Xilinx and from Xilinx Alliance Program member Xylon—which makes the task of rapidly developing these advanced HMI-based embedded industrial control systems far easier. Duration: 60 mins
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