Floating-point C based blocks in System Generator for DSP - Live Webcast

Date/Time: On Demand

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Join Xilinx in a presentation where you will learn how to rapidly accelerate and integrate your floating-point single or double precision C algorithms in model-based designs by using Vivado High-Level Synthesis and System Generator for DSP. See a step-by-step example of how you can customize and optimize floating-point implementations in hardware.

With the introduction of the Vivado™ Design Suite, Vivado High-Level Synthesis (HLS) accelerates design implementation by enabling C, C++ and SystemC specifications to be directly targeted into All Programmable FPGAs, SoCs and 3D ICs without the need to manually create RTL. Xilinx System Generator for DSP™ accelerates production-quality model-based DSP designs implementation from MathWorks™ MATLAB and Simulink. The combination of Vivado HLS and System Generator provides system and design architects alike a methodology to accelerate algorithms in C while providing access to a comprehensive model-based simulation and verification environment.

What You Will Learn

  • How to rapidly accelerate floating-point single or double precision C algorithms by using Vivado High-Level Synthesis
  • How to integrate C based blocks in model-based design by using System Generator for DSP

Live Webcast Presented by Xilinx Technology Experts

Duncan Mackay
Senior Staff Products Applications Engineer, Xilinx Inc.

Vinay Singh
Senior Product Marketing Manager for Electronic System Level Design, Xilinx Inc.

About Xilinx Webcasts

Xilinx webcasts are 60 minute live broadcasts featuring interactive technical presentations, product demonstrations, and question-and-answer sessions presented by our expert silicon and software people on Xilinx technology, the industry, or both. All broadcasts are made available for on-demand viewing within 24 hours of the live session.




Zynq All Programmable SoC
Title Description Recording Info.
Zynq All Programmable SoC: Where ARM Processors Meet Hardware Programmability This second Zynq-7000 AP SoC webcast will provide the latest information on Zynq-7000 solutions including additional architectural details and an update on the rapidly expanding Zynq-7000 AP SoC ecosystem and infrastructure.
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Duration: 60 mins
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7 Series FPGAs
Title Description Recording Info.
Accelerating Productivity with Xilinx 7 Series Targeted Design PlatformsThis webinar will provide an introduction to the recently announced Xilinx Targeted Design Platforms for 7 series FPGAs. In addition to technical details of the new Kintex™-7 KC705 Evaluation Kit, Virtex®-7 VC707 Evaluation Kit and Kintex-7 FPGA DSP Kit, this broadcast will give a preview of the Xilinx 7-series platforms roadmap. Duration: 60 mins
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Virtex-6/Spartan-6 FPGAs
Title Description Recording Info.
Accelerate Your Industrial Application's Performance Using Xilinx FPGAs and National Instruments Tools Join Xilinx and National Instruments® and learn how Xilinx Spartan®-6 FPGA technology can be used to solve complex industrial applications that demand a high-performance hardware platform. During this 60 minute webcast, we will demonstrate how graphical system design can be implemented on this platform to enable rapid application development, verification and deployment to reduce costs and time to market. Duration: 60 mins
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Meeting the Power Requirements for Xilinx Spartan®-6 and Virtex®-6 Families This video explains how to meet the power requirements for Xilinx Spartan-6 and Virtex-6 Families, and introduces TI?s Fusion Digital Power? technology Duration: 8.50 mins
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Xilinx Development Platform and TI Power Solutions This video explains Xilinx?s Development Platform and Power Schemes using TI?s Fusion Digital Power ? Duration: 10 mins
TI Fusion GUI Demonstration This video demonstrates TI?s Fusion Digital Power? GUI in the Xilinx Development Platform Duration: 8.5 mins
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Creating Power-Optimized Designs with Virtex-6 and Spartan-6 FPGAs As an alternative to ASICs and ASSPs, FPGAs enable manufacturers of digital electronic systems to accelerate new products to market and increase product differentiation while reducing cost and risk. The latest generation of FPGAs offer increases in performance, capacity, and built-in capabilities that make them suitable for implementing a greater portion of critical system-level functionality. Duration: 60 mins
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Title Description Recording Info.
Designing with the Embedded PowerPC 440 in Xilinx's Virtex®-5 Webcast Duration: 60 mins
Achieve Breakthrough Performance with the New PowerPC® Processing Block Architecture The new Virtex®-5 FXT family of Xilinx FPGAs was developed specifically to enable integration of sophisticated embedded systems on a single, flexible and high performance platform. In this webcast, Xilinx will introduce the high system performance and bandwidth advantages of the innovative PowerPC 440 blocks embedded in the new Virtex-5 FXT platform FPGAs. We will show how to build customized embedded systems to unique and exacting design requirements, while lowering both system cost and power consumption. FPGA-based embedded processing designs, reduce component count, board size and ultimately simplify the Bill of Materials without giving up performance. Duration: 60 mins
Multi Gigabit Serial I/O with Virtex-5 FXT Webcast Duration: 60 mins
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Duration: 60 mins

Xilinx Virtex®-5 FPGA Power Optimization &Power Design Guidelines Learn how to leverage the dedicated blocks in Virtex®-5, FPGAs using the Xilinx Power Estimator (XPE) tool .

Duration: 60 mins

Virtex-5 Power Estimation and Measurement Demonstration

In this demonstration, we look at the steps required to create an accurate power estimate for Virtex®-5 devices using the XPower Estimator (XPE) tool. We then demonstrate the low power consumption characteristics of Virtex-5 devices by taking actual measurements on an ML550 board, the preferred platform for making detailed power measurements.

Format: WMV
Size: 50MB
Duration: 36 mins

Design Tools
Getting Started
Title Description Recording Info.

Xilinx FPGA Design Using RTL-based projects with PlanAhead Design and Analysis Tool


Xilinx FPGAs are currently designed using the ISE design suite of tools, which allow design entry, synthesis, verification, and implementation functions to generate a working bit file. Traditionally, Project Navigator is the graphical front end (GUI) tool which users use to create and manage projects and execute compilation flows to generate a bit file. PlanAhead is an alternative tool that can be used in a similar capacity and offers a number of advantages. These advantages include easy-to-use and powerful pin planning, floorplanning, design analysis and debug capabilities. This webinar will go into technical depth on the use of PlanAhead for designing Xilinx FPGAs. We will guide you through creating a design using RTL design entry, utilizing Xilinx IP Repository, verifying functionality with ISE Simulator, synthesizing with XST, IO assignment, inserting debug logic for ChipScope, implementing the design with various tool option strategies, floorplanning for timing closure, generating a bitstream file, and launching iMPACT and ChipScope Analyzer to program and debug a device. Duration: 60 mins

Achieve Higher FPGA Design Productivity with Plug and Play IP


Today, more than ever, FPGAs are a platform for developing advanced system-on-a-chip products. Engineers are integrating more functionality than every before enabled by larger capacity FPGAs that include high-speed serial transceivers, high performance clocking, and signal processing. With this integration comes the desire to leverage available IP for common functions such as memory interfacing, encoding/decoding, processing, and more. The challenge - IP is available from third party providers but without a common interface with devoted resources to link and tie IP together and then verify that it works within the designer's system. Now there is a better way. Xilinx has helped to define the AXI4™ interface, a common interconnect that enables customers to easily link and combine IP within an FPGA. Even better news - it's available now. Format: FLV
Duration: 60 mins
Unlock New Levels of Productivity for your Next FPGA Design In this webcast you will learn that the Xilinx ISE Design Suite 12 is the production-optimized tool suite for Virtex-6 and Spartan-6 FPGAs that delivers innovation in three critical areas of concern for FPGA design: power reduction, productivity and performance. This webcast will present an overview of key achievements and advances in each of these three categories. This webcast will also describe the next generation Partial Reconfiguration design flow to help designers reduce the size, cost and power consumption of a design. Format: WMV
Duration: 60mins

ISE Design Suite 11 – Software Products and Licensing


This video will introduce you to the different configurations in the ISE Design Suite and describe the different Xilinx licensing options. Format: WMV
Duration: 36 mins
ISE Design Suite: Logic Edition – A Quick Tour This video demonstration provides a quick tour of the key highlights and capabilities of the ISE Design Suite: Logic Edition and how it is used in typical design scenarios. After watching this video, the viewer should have a good understanding of the main steps to get a design through the entire tool chain: from HDL entry, to place and route, all the way through to bitstream generation. Common tasks of pin-assignment, timing constraint specification will also be covered. The viewer will see the most relevant places to analyze and visualize the results of processing. Format: WMV
Duration: 36mins
Quick Tour of the PlanAhead Design Environment With the release of the ISE Design Suite 11, all ISE Design Suite configurations include the PlanAhead design analysis tool. This video highlights new features and technologies to help you get the most out of PlanAhead. Format: WMV
Duration: 33 mins
How to Use ISE Simulator (ISim) This short video demonstration shows how to use ISE Simulator (ISim) for simulating an HDL-based design. The demonstration goes over basic simulation steps in order to effectively verify design functionality via HDL simulation. Format: WMV
Duration: 31 mins
How to Debug a Design Using ChipScope Pro This video takes you through the various methods of adding ChipScope cores to an FPGA design, implementing the design, and interacting with the ChipScope cores in the design in the device-under-test. This video also highlights new ChipScope features that are available in the ISE Design Suite 11 release. Format: WMV
Duration: 51 mins
ISE Design Suite – RTL / Technology Schematic Viewers The ISE Design Suite 11 introduces a new RTL / Technology Viewer, which fully integrated in ISE design environment. This new Viewer has faster schematic rendering as well as many debug features. The new key features include: logic cones extraction, selective block analysis, return to previous schematic, support of multiple schematics of the same netlist etc. This video demonstration will highlight new RTL / Technology Viewer features and how to use them for design analysis. Format: WMV
Duration: 23 mins
An Overview of Device Configuration using iMPACT This video describes the configuration and verification capabilities available within the iMPACT tool. Users will be shown the configuration methods for many supported modes and targets, as well as programming file generation for a variety of formats. The iMPACT GUI and the redesigned PROM File Formatter will be highlighted, but batch/command line features will also be demonstrated. Format: WMV
Duration: 15 mins
What's New
Title Description Recording Info.
Optimize Your FPGA System for Cost, Power, and Flexibility Using Partial Reconfiguration This webcast talks describes how Xilinx Partial Reconfiguration technology allows designers to change functionality on the fly, eliminates the need to fully reconfigure and re-establish links, dramatically enhances the flexibility that FPGAs offer. Radio, video or bus links or other vital functions can remain established while other functions are reloaded on demand. Duration: 60 mins
Productivity Enhancements in the ISE Design Suite: Logic Edition 11 This video demonstration covers some of the main highlights of what is new in ISE Design Suite 11: Logic Edition. It will discuss key improvements made in all aspects of the tool chain from ISE Project Navigator, the implementation tools and integration of ChipScope and PlanAhead Format: WMV
Duration: 37 mins
What’s New in PlanAhead 11.1 This video demonstration describes the new features available with the latest release of the PlanAhead design analysis tool. This demonstration highlights the improved design flow integration of PlanAhead with the ISE Project Navigator, synthesis and implementation, I/O pin planning, and verification with ChipScope pro. Format: WMV
Duration: 33 mins
Title Description Recording Info.
ISE Design Suite 11 – The Design Methodology for Targeted Design Platforms Dramatic shifts in the economic and technical landscape combined with demanding technical requirements are driving the ever-increasing adoption of FPGAs in the heart of digital electronic systems. ‘Targeted Design Platforms’, built on an FPGA foundation, directly address the competing needs of higher performance, streamlined power consumption and reduced system cost by integrating software and hardware components that enable designers to accelerate innovation.

Duration: 60 mins

Memory Interface Design with MIG 3.3 This 28 minute video product demonstration provides an overview of the Xilinx solutions for memory interfaces and the features and benefits of the Memory Interface Generator (MIG) 3.3 design tool. Format: WMV
Size: 43MB
Duration: 28 mins
Build a MicroBlaze Custom Embedded Processing System in Just Minutes This demonstration clearly presents how to use the award winning Platform Studio tool suite to customize a MicroBlaze™ soft processing solution, including peripheral selection and co-processing acceleration. Format: WMV
Size: 92MB
Duration: 58 mins
Designing Embedded Systems With Linux and Low Cost FPGAs Through lowest system cost, cost-efficient logic design and low-cost complex computation and embedded processing, this chalk talk examines how Extended Spartan-3A FPGAs are the lowest total cost solution available. Format: SWF
Duration: 20.24 mins
I/O Pin Planning with PinAhead Technology This video demonstration explains the process of I/O assignments of the PlanAhead pin planning capabilities, highlighting the process of managing the entire I/O pin planning process for early and optimized port management for better FPGA and PCB design results. Format: WMV
Duration: 26 mins
ISE Power Solution This video is about the ISE software solution designed to help our customers to plan, analyze and optimize the power consumed by Xilinx FPGAs Format: WMV
Duration: 15 mins

Optimize Results Using Design Goals & Strategies and SmartXplorer


Video Demonstration Format: WMV
Duration: 31 mins
Debugging Designs with PlanAhead and ChipScope Pro This video demonstrates the various methods of adding ChipScope Pro cores to an FPGA design, implementing the design, and interacting with the ChipScope Pro cores in the design in the device-under-test. This video also highlights new ChipScope Pro features that are available in the ISE Design Suite 11 release. Format: WMV
Duration: 21 mins

Improve Design Performance with the PlanAhead Design and Analysis Tool

Xilinx PlanAhead Design and Analysis Tool Format: WMV
Duration: 35 mins
Using Multiple Constraint Files Video Demonstration Format: WMV
Duration: 12 mins
Using 7Circuits and PlanAhead for FPGA-Based System Design Designers of FPGA-based systems often struggle with achieving pin assignment closure that satisfies the needs of both the FPGA and the PCB on which the FPGA’s reside. Used together, PlanAhead and 7Circuits offer a compelling solution, ensuring that the FPGA’s internal resources have been properly utilized and that the chosen pin assignments are optimized for PCB routing. This video explores the challenges designers of FPGA-based systems face and, through a short demo, how a 7Circuits/PlanAhead flow can assist the team in overcoming those challenges. Format: WMV
Duration: 18 mins
Xilinx Embedded Technologies
Title Description Recording Info.
Using Xilinx Platform Studio in ISE Design Suite 11 In addition to new features in the Xilinx Platform Studio (XPS) 11, this video describes the recommended hardware and software design flows. Viewers will also learn the steps required to export hardware projects to the Software Development Kit. Duration: 10 mins
Using Base System Builder in ISE Design Suite 11 This video will demonstrate how Base System Builder (BSB) can quickly create an embedded processor subsystem for use in your Xilinx FPGA design. Duration: 8 mins
Introduction to the Xilinx Software Development Kit This video explains features and benefits of the Software Development Kit available in the ISE Design Suite: Embedded Edition and as a stand-alone product. Duration: 5 mins
Quick Start Embedded Software Development With MicroBlaze and Spartan-3A FPGAs Webcast Duration: 60 mins
Embedded Networking With MicroBlaze and Spartan-3A FPGAs Webcast Duration: 60 mins
Designing Embedded Systems With Linux and Low-cost FPGAs In this Chalk Talk Webcast, Xilinx and LynuxWorks chat with Amelia Dalton of FPGA Journal about the increasing challenges of designing connected embedded systems and how to solve some of them with flexible hardware and software platforms.
Duration: 60 mins
DSP Solutions
Title Description Recording Info.
Leveraging the Performance Advantages of FPGAs for DSP and Video Applications This webinar will explore how designers can use exclusive hardware and software technologies from Xilinx to accelerate high-performance DSP and Video applications using target design platforms. These platforms combine development boards, design tools, IP, reference designs and partnerships into complete DSP development solutions that let you focus on the competitive differentiation of your designs. Duration: 60 mins
Xilinx DSP Design Platforms: Achieving 1000 GMACs of DSP performance with Xilinx FPGAs Learn how FPGAs can be used to deliver 30X the DSP processing horsepower per dollar over a traditional DSP. Learn how the Xilinx Spartan-6 and Virtex-6 FPGA DSP kits help users new to FPGAs or new to using FPGAs for DSP adopt FPGAs for their high-performance DSP processing needs. Duration: 60 mins
Power Estimation in a High-Level DSP Design Flow Join Amelia Dalton as she talks with Tim Vanevenhoven of Xilinx about new methods for estimating and reducing power consumption in FPGA-based DSP designs. Duration: 13 mins
DSP System Design on FPGAs Using the ISE® Design Suite 10.1 Webcast Duration: 60 mins
Improve DSP Design Productivity Using ISE® and System Generator for DSP 10.1 This video product demonstration provides an overview of the new integration between Xilinx System Generator and Xilinx ISE® Project Navigator design environment. Format: WMV
Size: 9MB
Duration: 10 mins
Accelerating FPGA Designs with AccelDSP™ and System Generator for DSP™ This 30 minute video demonstration gives an overview of the DSP design tools offered by Xilinx. We begin in AccelDSP™ with a floating-point MATLAB® algorithm, and generate a VHDL or Verilog model along with a test bench. Format: WMV
Size: 49MB
Duration: 30 mins
System Generator for DSP System Generator for DSP—our high-level modeling environment for DSP data paths—yields performance and efficiency comparable to hand-crafted designs. Format: WMV
Size: 72MB
Duration: 51 mins
FPGAs for Signal Processing This Demo shows you how an FPGA device can be used for signal processing and provides an overview of the Xilinx DSP solution including the IP cores that are available as algorithms and DSP software. Format: WMV
Size: 36MB
Duration: 39 mins
Spectrum Channelization This module explains spectrum channelization for wired and wireless applications using a number of examples built using the Xilinx System Generator for DSP and the Xilinx DSP IP library. Format: WMV
Size: 29MB
Duration: 27 mins
Designing QAM Demodulators This compelling Demo shows the implementation of a QAM receiver including both synchronization and adaptive channel equalization. Format: WMV
Size: 36MB
Duration: 30 mins
Spectrum Channelization This module explains spectrum channelization for wired and wireless applications using a number of examples built using the Xilinx System Generator for DSP and the Xilinx DSP IP library. Format: WMV
Size: 29MB
Duration: 27 mins
Xilinx DSP Development Using System Generator This presentation will show how you can significantly enhance productivity when developing signal processing systems using Xilinx System Generator. Format: WMV
Size: 18MB
Duration: 14 mins
Hardware Co-Simulation Basics using System Generator for DSP This video explains the advantages and basic steps for performing hardware co-simulation using System Generator for DSP including a description of available interface protocols. Format: WMV
Size: 15MB
Duration: 13 mins
Real-time Hardware Co-Simulation This video demonstration describes the steps required to perform real-time hardware co-simulation using System Generator for DSP and the ISE Design Suite: System Edition. An example is provided targeting the Xilinx ML605 Targeted Design Platform. Format: WMV
Size: 13MB
Duration: 11 mins
Simulink-Based FPGA Power Analysis for System Generator for DSP This video describes the integration of the Xilinx XPower Analyzer with System Generator and how users can use this combination to analyze power within their DSP design. An example is provided showing a complex filter targeting a Virtex-6 device to show how users can evaluate different filter architectures and obtain power analysis in addition to other QoR metrics. Format: WMV
Size: 14MB
Duration: 12 mins
System Generator Deployment and Installation on Linux This video demonstrates the installation of System Generator for DSP on the Linux platform. This includes an overview of the installation options available for individual users and system administrators as well as managing startup script files. Format: WMV
Size: 10MB
Duration: 8 mins
Title Description Recording Info.
Designing Cost-effective, Greener LTE Basestations with Xilinx FPGAs Exponential growth in mobile data has fuelled enormous interest in 4G wireless technology such as LTE. However, the increased processing constraints placed provide a significant challenge in meeting the dual imperatives of base station cost and power reduction. This webcast will describe how Xilinx FPGAs and IP help resolve these issues, providing a scalable and reconfigurable platform for base station development. Duration: 60 mins
Accelerate System Design Innovation and Slash Infrastructure Development Time with FPGA-Based Targeted Design Platforms Base Targeted Design Platforms combine with optimized development tools to enable simpler and smarter design methodologies for creating FPGA-based system-on-chip solutions targeting a wide variety of markets and applications. Duration: 60 mins
Digital Wireless Test Revolution as Illustrated by DigRF V3 Spartan® &Virtex® platform FPGAs, provide the versatility required to support new over air standards Duration: 60 mins
Title Description Recording Info.
Building Optically Compliant High Performance Serial Links at 10G, 100G and 400G In order to meet increasing bandwidth demands, communication equipment vendors are building 40G, 100G and looking toward to the next generation 400G systems with as few changes to the existing infrastructure as possible. They demand more of the Programmable Platforms and semiconductor chips that interface with the optical modules both in terms of functionality as well as performance to double bandwidth capacity, to maintain power density and to lower costs. This webcast elaborates on the design requirements—architecture, circuit techniques, and system level considerations—to build optically compliant serial interfaces for the 40G/100G and 400G systems. Duration: 60 mins
Accelerating High-Bandwidth System Design Implementations with FPGA-based platforms Attend this webcast and learn how the Targeted Reference Design, delivered through the Xilinx Connectivity Kits, jumpstarts application development by providing a complete design flow for a end-to-end system application hardware design and RTL source files, simulation environment, implementation flows and scripts, software device driver source files, performance / status monitor application and documentation Duration: 60 mins
Addressing the Performance Bottleneck in Modern SOC Design - Serial IO Connectivity This web seminar covers Xilinx's comprehensive serial IO portfolio which addresses challenging System-on-Chip requirements across the serial performance spectrum, from mainstream through ultra high-end applications. In addition to implementing optimized transceivers across high-volume FPGA applications, Xilinx reveals how we are extending the high-performance end of the serial connectivity portfolio. Duration: 60 mins
Direct Memory Access (DMA) for PCI Express on Xilinx Virtex-6 and Spartan-6 FPGAs PCI Express® has increased the chip-to-chip bandwidth possible for PCI based systems. With PCI Express v2.0, also commonly referred to as Gen2, becoming mainstream this year these bandwidth intensive applications can be tackled with Xilinx Virtex-6 Integrated Blocks for PCI Express. Xilinx second generation of integrated blocks builds on the experience from Virtex-5 to deliver the most robust and extremely high-performance PCI Express interface. Duration: 60 mins
Smarter Vision
Title Description Recording Info.
Seeing is Believing: Develop High-Performance Machine Vision Systems Faster than the Blink of an Eye In this webinar, Xilinx and Silicon Software explore an embedded machine vision design approach that addresses the many challenges and the performance requirements of 21st-century machine vision. This webinar will provide concrete benchmark data that sharply contrasts the performance of a pure software implementation versus one that’s been accelerated with hardware. The webinar will also introduce easy-to-use tools that can help you design and deploy a hardware/software system that meets all of your machine vision system requirements. Duration: 60 mins
How to Drive Multiple Live Cameras and Displays for Pennies The MIPI Display Serial Interface (DSI) and Camera Serial Interface 2 (CSI-2) are becoming key, low-cost industry standards for connecting video displays and cameras to a wide variety of embedded systems. You can now incorporate these MIPI interfaces into FPGA-based systems. Want to know more? Xilinx and its Alliance members Xylon and Northwest Logic present a webinar to help you design MIPI’s DSI and CSI-2 interfaces into your next system at a surprisingly low cost. If your system must fuse video streams from multiple cameras or if you need to drive multiple displays—even 4K cameras and displays—then this webinar is especially for you. Working with video in automotive systems? You will also want to see this webinar because of the low-cost aspects of the MIPI video interfaces. Duration: 60 mins
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