Example: Direct I/O in an SDSoC Platform

An SDSoC platform can include input and output subsystems, e.g., analog-to-digital and digital-to-analog converters, or video I/O, by converting raw physical data streams into AXI4-Stream interfaces that are exported as part of the platform interface specification. In "Using External I/O" the SDSoC Environment User Guide: An Introduction to the SDSoC Environment (UG1027) includes a discussion of the zc702_axis_io sample platform. This example includes sample applications that demonstrate how an input data stream can be written directly into memory buffers without data loss, and how an application can "packetize" the data stream at the AXI transport level to communicate with other functions (including, but not limited to DMAs) that require packet framing.

Remember: The source code for this platform can be found in <sdx_root>/samples/sdspfm/zc702_axis_io.

The hardware component of an SDSoC platform is represented in a Vivado project which is located in the src/vivado subdirectory. In an SDx Terminal shell, you can view the block diagram by opening the Vivado project using the command, vivado zc702_axis_io.xpr and clicking Open Block Design on the left in the Flow Navigator.

Figure: zc702_axis_io Block Diagram



Instead of live I/O from off-chip, this platform contains a free-running binary counter that generates a continuous stream of data samples at 50 MHz, which acts as a proxy for data streaming directly from FPGA pins. To convert this input data stream into an AXI4 stream for SDSoC applications, the platform connects the counter output to the s_axis_tdata slave port of an AXI4-Stream data FIFO, with a constant block providing the required s_axis_tvalid signal, always one. The data FIFO IP is configured to store up to 1024 samples with an output clock of 100 MHz to provide system elasticity so that the consumer of the stream can process the stream "bubble-free" (i.e., without dropping data samples). In a real platform, the means for converting to an AXI4 stream, relative clocking and amount of hardware buffering will vary according to system requirements.

Like input streaming off of an analog-to-digital converters, this data stream is not packetized, so in the AXI4 stream there is no TLAST signal. This means that any SDSoC application that consumes the data stream must be capable of handling unpacketized streams. Within the SDx environment, all data mover IP cores other than zero_copy require packetized streams, so to consume streaming input from this platform, an application must employ direct connections to the AXI4-Stream port.
Note: A platform can also export an AXI4 stream port that includes the TLAST signal, in which case SDSoC applications do not require direct connections to the port.
Remember: In this release of the SDx environment, all exported AXI and AXI4-Stream platform interfaces must run on the same “data motion” clock (dmclkid). If your platform I/O requires a clock that is not one of the exported SDx platform clocks, you can use the AXI4-Stream Data FIFO IP within the Vivado IP catalog for clock domain crossing.