CORE Generator™ Documentation

CORE Generator Simulation Compile Scripts
CORE Generator 3.1i User Guide

This release includes IP and CORE Generator software updates for the Xilinx 3.x software. It is recommended that you install the latest 3.x Xilinx Software Service Pack.

Note: To access the IP Update download files, you will be asked to Register (once) and then sign-in to the IP Download Lounge. 

View: 3.x IP Update #4 Installation Instructions & Release Notes

Register: Register for the IP Update Lounge

Download: IP Update #4 zip and tar files

Download: MXE Libraries
 
 

MEMORIES AND STORAGE ELEMENTS 

• Content Addressable Memory (CAM) (V1.0) 
• Asynchronous_FIFO (V3.0) 
• Synchronous FIFO (V2.0)
• Distributed Memory(V4.1) 
• Dual-Port Block Memory (V3.2) 
• Single-Port Block Memory (V3.2) 

 

DIGITAL SIGNAL PROCESSING

• Cascaded Integrator-Comb(CIC) Filter (V1.0)
• Bit Correlator (V2.0)
• Distributed Arithmetic FIR Filter (V5.0)
• Direct Digital Synthesizer (DDS) (V3.1)
• LFSR (V1.0)

COMMUNCATIONS & NETWORKING

• 8B/10b Encoder (V1.0)
• 8b/10b Decoder (V2.0)
• Convolutional Encoder (V1.0)

MATH FUNCTIONS

• Sine/Cosine Look Up Table (V3.0)
• Variable Parallel Virtex Multiplier (V2.0)
• Dynamic Constant Coefficient Multiplier (V2.0)
• Pipelined Divider (V2.0)
• Multiply Accumulator (V1.1)
• Multiply Generator (V3.1)
• Accumulator (V4.0)
• Adder/Subtracter (V4.0)

BASIC ELEMENTS 

• Comparator (V4.0)
• Binary Counter (V4.0)
• Binary Decoder (V4.0)
• Bit Bus Gate (V4.0)
• Bit Gate (V4.0)
• Bus Gate (V4.0) 
• Bit Multiplexer (V4.0)
• Bus Multiplexer (V4.0)
• BUFE-based Multiplexer Slice (V4.0)
• BUFT-based Multiplexer Slice (V4.0) 
• FD-based Parallel Register (V4.0)
• LD-based Parallel Latch (V4.0)
• FD-based Shift Register (V4.0) 
• RAM-based Shift Register (V4.0) 
• LFSR (V1.0) 

 

VIDEO & IMAGE PROCESSING

• 1-D Discrete Cosine Transform (DCT) (V1.0)

Comments, Questions, or Problems? Please E-mail coregen@xilinx.com or enter a Web case.