ISE / Vivado IP Updates
Key Documentation
Quick Links
New Device Family Support
Public access support for the Zynq™-7000, device families has been added to a selection of cores in this release.
For a comprehensive listing of IP cores supporting these new device families, click the "IP in this Release" tab on this page.
AXI4 Support
New AXI4 IP
For a full listing of Xilinx AXI4 IP see www.xilinx.com/ipcenter/axi4_ip.htm
For more information on AXI4 at Xilinx see www.xilinx.com/ipcenter/axi4.htm
New IP Cores
The release also includes the following new LogiCORE IP:
- Audio, Video and Image Processing
- Bus Interface and IO
- Embedded Processing
- FPGA Features and Debug
Updated IP Cores
This release includes updates to these other popular IP cores:
- Building Block IP
- Architecture Wizards*
- Block Memory Generator*
- FIFO Generator*
- Memory Interface Generator (MIG)*
- Connectivity
- PCI Expres
- FPGA Features and Debug
- 7 Series FPGAs Transceivers Wizard
- Clocking Wizard
- XADC Wizard
*Included at no additional charge with ISE and Vivado
**Included at no additional charge with EDK
| New Cores | Additional License Required | Datasheet (PDF) | AXI4 | Vivado | Spartan-6 | Virtex-5 | Virtex-6 | Virtex-7 | Virtex-7-HT | Kintex-7 | Artix-7 | Zynq-7000 | Release Note (PDF) |
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| Video, Audio & Image Processing | ||||||||||||||||||
| Test Pattern Generator* (v4.00a) |  |
PG0103 | AXI4-Stream
AXI4-Lite |
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XTP025 | |||||||
| Bus Interface and IO | ||||||||||||||||||
| SPDIF Controller (v1.2) | |
PG045 | AXI4-Stream
AXI4-Lite |
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XTP025 | |||||||
| Embedded Processing | ||||||||||||||||||
| AXI Exerciser * (v4.00a) | PG094 | AXI4 | |
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XTP025 | ||||||||||
| AXI Thin Film Transister (TFT) Controller * (v1.00a) | PG095 | AXI4
AXI4-Lite |
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XTP025 | ||||||||||
| FPGA Features & Debug | ||||||||||||||||||
| AXI Protocol Checker* (v1.0) | PG101 | AXI4
AXI4-Lite AXI3 |
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XTP025 | |||||||||||
| New Core Versions | Additional License Required | Datasheet (PDF) | AXI4 | Vivado | Spartan-6 | Virtex-5 | Virtex-6 | Virtex-7 | Virtex-7-HT | Kintex-7 | Artix-7 | Zynq-7000 | Release Note (PDF) |
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| Audio, Video & Image Processing | ||||||||||||||||||
| Image Characterization (v3.00a) | |
PG015 (AXI) | AXI4-Stream
AXI4-Lite |
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XTP025 | ||||||
| Image Edge Enhancement (v6.00a) | |
PG003 (AXI) | AXI4-Stream
AXI4-Lite |
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XTP025 | ||||||
| Motion Adaptive Noise Reduction (v5.01a) | |
PG006 (AXI) | AXI4-Stream
AXI4-Lite |
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XTP025 | ||||||
| Object Segmentation (v3.00a) | |
PG018 (AXI) | AXI4-Stream
AXI4-Lite |
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XTP025 | ||||||
| On-Screen Display (v5.01a) | |
PG010 | AXI4-Stream
AXI4-Lite |
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XTP025 | ||||||
| AXI Video DMA (AXI VDMA) */** (v5.04a) | PG020 (AXI) | AXI4
AXI4-Stream AXI4-Lite |
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XTP025 | |||||||
| Automotive & Industrial | ||||||||||||||||||
| CAN (v4.2) | |
PG096 (AXI) | AXI4-Lite | |
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XTP025 | ||||||
| Basic Logic | ||||||||||||||||||
No updates were shipped for Basic Logic cores |
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| Communications & Networking | ||||||||||||||||||
| Aurora | Additional License Required | Datasheet (PDF) | AXI4 | Vivado | Spartan-6 | Virtex-5 | Virtex-6 | Virtex-7 | Virtex-7-HT | Kintex-7 | Artix-7 | Zynq-7000 | Release Note (PDF) |
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| Aurora 8B/10B * (v8.3) | PG046 | AXI4-Stream | |
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XTP025 | ||||||||
| Aurora 64B/66B * (v7.3) | PG074
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AXI4-Stream | |
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XTP025 | ||||||||||
| Error Correction | ||||||||||||||||||
| Soft Error Mitigation (SEM) Core * (v3.4) | PG036 | |
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XTP025 | |||||||||
| Ethernet | ||||||||||||||||||
| 10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation for Backplanes (10GBASE-KR) (v2.6) | |
PG068 | |
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XTP025 | ||||||||||||
| 10 Gigabit Ethernet PCS/PMA (10GBASE-R) * (v2.6) | PG068 | |
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XTP025 | ||||||||||||
| 10 Gigabit Ethernet Medial Access Controller (10GEMAC) (v11.5) | |
PG072 | AXI4-Stream
AXI4-Lite |
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XTP025 | ||||||
| Ethernet 1000BASE-X PCS/PMA or SGMII (1000BASE-X) * (v11.5) | PG047 | |
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XTP025 | ||||||||
| SMPTE2022-5/6 Video Over IP (v2.1) | |
PG023 | AXI4
AXI4-Stream AXI4-Lite |
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XTP025 | |||||||||
| Tri-Mode Ethernet Media Access Controller (TEMAC) (v5.5) | |
PG051 | AXI4-Stream
AXI4-Lite |
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XTP025 | ||||||
| Wireless | Additional License Required | Datasheet (PDF) | AXI4 | Vivado | Spartan-6 | Virtex-5 | Virtex-6 | Virtex-7 | Virtex-7-HT | Kintex-7 | Artix-7 | Zynq-7000 | Release Note (PDF) |
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| CPRI (PC-CFR) (v6.1) | |
PB012 | AXI4-Lite | |
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XTP025 | ||||||
| JESD204 (v3.1) | |
PB011 | AXI4-Stream
AXI4-Lite |
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XTP025 | ||||||||
| Peak Cancellation Crest Factor Reduction (PC-CFR) (v3.1) | |
PB008 | AXI4-Stream
AXI4-Lite |
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XTP025 | |||||||
| Digital Signal Processing | ||||||||||||||||||
No updates were shipped for Digital Signal Processing cores |
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| Embedded Processing | ||||||||||||||||||
| Additional License Required | Datasheet (PDF) | AXI4 | Vivado | Spartan-6 | Virtex-5 | Virtex-6 | Virtex-7 | Virtex-7-HT | Kintex-7 | Artix-7 | Zynq-7000 | Release Note (PDF) |
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| AXI External Memory Controller (AXI EMC)** (v1.03b) | PG100 | AXI4
AXI4-Lite |
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XTP025 | ||||||||
| AXI Interrupt Controller (AXI INTC)* (v2.00a) | PG099 | AXI4-Lite | |
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XTP025 | ||||||||
| AXI PCI Express (PCIe) ** (v1.06a) | PG055 | AXI4 | |
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| AXI Performance Monitor ** (v3.00a) | PG037 | AXI4 AXI4-Stream AXI4-Lite |
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XTP025 | ||||||||
| AXI Quad SPI ** (v2.00a) | DS843 | AXI4 AXI4-Lite |
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XTP025 | ||||||||
| AXI Streaming FIFO ** (v3.00b) | PG080 | AXI4
AXI4-Stream AXI4-Lite |
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XTP025 | ||||||||
| AXI System Cache * (v1.01c) | PG031 | AXI4
AXI4-Lite |
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XTP025 | ||||||||
| Fixed Interval Timer */** (v1.01c) | PG037 | |
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XTP025 | ||||||||
| FSL_V20 * (v2.11f) | DS449 | |
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XTP025 | |||||||||||||
| I/O Module * (v1.02b) | PG052 | |
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XTP025 | ||||||||
| LMB BRAM Interface Controller * (v3.10c) | PG061 | |
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XTP025 | ||||||||
| Mailbox * (v1.01b) | PG088 | AXI4-Stream
AXI4-Lite |
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XTP025 | |||||||
| FPGA Features & Design | ||||||||||||||||||
| 7 Series FPGAs Transceiver Wizard * (v2.4) | UG769 | |
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XTP025 | |||||||||||
| Clocking Wizard * (v4.4) | PG065 | |
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XTP025 | ||||||||
| XADC Wizard * (v2.4) | PG091 | AXI4-Lite | |
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XTP025 | ||||||||||
| Interconnect Infrastructure | ||||||||||||||||||
| Additional License Required | Datasheet (PDF) | AXI4 | Vivado | Spartan-6 | Virtex-5 | Virtex-6 | Virtex-7 | Virtex-7-HT | Kintex-7 | Artix-7 | Zynq-7000 | Release Note (PDF) |
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| AXI Central DMA Controller ** (v3.04a) | PG034 (AXI) | AXI4
AXI4-Lite |
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XTP025 | ||||||||
| AXI Chip2Chip (v3.00a) | PG067 (AXI) | AXI4
AXI4-Lite |
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XTP025 | |||||||||||
| AXI DMA Controller ** (v6.03a) | PG021 (AXI) | AXI4
AXI4-Stream AXI4-Lite |
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XTP025 | |||||||
| AXI Datamover * (v4.02a) | PG022 (AXI) | AXI4
AXI4-Stream |
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XTP025 | ||||||||
| AXI Stream Interconnect * (v1.1) | PG035 | AXI4-Stream | |
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XTP025 | ||||||||
| Math Functions | ||||||||||||||||||
| Floating Point Operator * (v6.2) | PG060 | AXI4
AXI4-Lite |
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XTP025 | |||||||
| Memories & Storage Elements | ||||||||||||||||||
| Block Memory Generator * (v7.3) | PG058 | AXI4
AXI4-Lite |
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XTP025 | |||||||
| Distributed Memory Generator * (v7.2) | PG057 | |
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XTP025 | |||||||
| FIFO Generator * (v9.3) | PG057 | AXI4
AXI4-Stream AXI4-Lite |
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XTP025 | ||||||
| Memory Interface Generator * (MIG) (v3.92 / 7 Series v1.8) | MIG 7 Series | AXI4 | |
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XTP025 | ||||||
| Standard Bus Interfaces | ||||||||||||||||||
| Additional License Required | Datasheet (PDF) | AXI4 | Vivado | Spartan-6 | Virtex-5 | Virtex-6 | Virtex-7 | Virtex-7-HT | Kintex-7 | Artix-7 | Zynq-7000 | Release Note (PDF) |
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| PCI Express® | ||||||||||||||||||
| AXI PCI Express (PCIe) ** (v1.06a) | PG055 | AXI4 | |
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XTP025 | ||||||||
| Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe) * (v1.4) | PG023 | AXI4-Stream | |
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XTP025 | |||||||||||||
| 7 Series Integrated Block for PCI Express (PCIe) Gen 2* (v1.8) | PG054 | AXI4-Stream | |
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XTP025 | ||||||||||
| RapidIO | ||||||||||||||||||
| Serial RapidIO Gen2 (v1.6) | |
PG007 | AXI4-Stream
AXI4-Lite |
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XTP025 | |||||||
*Included with ISE and/or Vivado as indicated at no additional charge
**Included with EDK at no additional charge
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