DVB-S.2 FEC Encoder LogiCORE IP Offerings & System Requirements
| This page lists the core configurations included with your purchase of the Xilinx DVB-S.2 FEC Encoder LogiCORE™ IP products, along with detailed information on System Requirements. | ||||
| System Requirements | ||||
| LogiCORE™ | Version | Software Support | Supported Devices | |
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DVB-S.2 FEC Encoder |
v1.4 |
ISE® 10.1 SP2 ISE IP Update 10.1.2 |
Virtex®-5, Virtex-4, Virtex-II Pro, Virtex-II Spartan®-3A, Spartan-3AN, Spartan-3A DSP, Spartan-3E, Spartan-3 |
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Hardware Evaluation Time Out Period A Hardware Evaluation license for the DVB-S.2 FEC Encoder LogiCORE™ IP core will enable you to parameterize, generate and instantiate this cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware. The IP cores will be fully functional in the programmed device for approximately 2 - 3 hours. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again |
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| Download the software requirements from the Software Updates page if you have not already done so. | ||||
| Required Patches | ||||
| Check the IP Release Notes Guide for information on any required patches. | ||||