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HDLC Single Channel Controller High Level Data Link Controller Overview:
The Xilinx HDLC LogiCORE™ IP allows a designer to tailor the HDLC to suit their application by setting certain parameters to enable/disable features.

HDLC exists in layer 2 of the OSI model which is the data link layer. HDLC uses zero insertion/deletion process (commonly known as bit stuffing) to ensure that the bit pattern of the delimiter flag does not occur in the fields between flags. The HDLC frame is synchronous and therefore relies on the physical layer to provide a method of clocking and synchronizing the transmission and reception of frames.

Xilinx provides a Single Channel and a Multi (256) Channel HDLC Controller as LogiCORE Interface Intellectual Property (IP) solutions.

Please read the pdf LogiCORE IP Site License Agreement

HDLC Features:
The OPB HDLC interface is a soft IP core designed for Xilinx FPGAs and contains the following features:

  • Support for a single independent full duplex HDLC channel.
  • Receive memory buffer of selectable depth.
  • Transmit FIFO of selectable depth.
  • Selectable 8/16 bit address receive address detection.
  • Selectable receive frame address discard
  • Selectable receive broadcast address detection. Broadcast address = 0xFF.
  • Selectable 16 bit (CRC-CCITT) or 32 bit (CRC-32) frame check sequence
  • 16 bit CRC error counter
  • 16 bit Aborted frame counter
  • Multiple Interrupts including:
  • Rx FCS error interrupt
    • Rx frame alignment error interrupt
    • FIFO overrun/underrun interrupts
    • Interrupt generated when either error counter rolls over
  • Tx frame abort control
  • Memory mapped direct I/O interface to registers and FIFOs as well as DMA and Scatter/Gather DMA capabilities for low processor and bus utilization.
  • 16 entry deep FIFOs for the Transmit Length, Receive Length, Transmit Status and Receive Status registers to support multiple packet operation.
  • Flag sharing between back to back frames

HDLC Software & License Requirements:
You must install Xilinx Embedded Development Kit (EDK) 3.2 with the latest service pack and the ISE™ 5.2i CD. This core is distributed as an evaluation IP and installed as part of the EDK CD. When Initially installed it will operate as an evaluation version with a evaluation license. To get a Full License, you will need to buy, register and download a Full license for this LogiCORE.

  • Updates to ISE 5.2i including service pack's are available.

  • Updates to EDK 3.2 including service pack's are available.
  


Data Sheet (PDF)
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