Xilinx provides two ways to evaluate this LogiCORE™ IP core: Simulation Only, and Full System Hardware Evaluation.
Please refer to the Requirements link on the product page for this core for details on System Requirements for the CORE Generator and EDK configurations of this core.
Please note that the conditions of the CAN LogiCORE IP Evaluation License Agreement apply toward your evaluation of this core.
To perform a Simulation Only Evaluation:
To perform a Full System Hardware Evaluation: The procedures are the same as for the Simulation Only Evaluation, except that for the CORE Generator configuration of the core, you must additionally request and install a Full System Hardware Evaluation license key. This will allow you to generate a bitstream that you can use to program a Xilinx FPGA and evaluate the core in hardware for a limited amount of time.
| Contact your local Xilinx FAE to submit a request to evaluate this core. If you do not already have a local FAE, your local Xilinx Sales Office can assign one to you. When your evaluation request is approved, follow the instructions from Xilinx Customer Service to generate a Full System Hardware Evaluation License key. Generate and install the key as directed by the instructions in the email you will receive. |
IP Evaluation license keys in EDK are pre-programmed with a 14-month evaluation period which starts from the official release date of your particular version of EDK. You can generate EDK systems containing these Full System Hardware Evaluation cores throughout the 14-month evaluation period. When programmed into an FPGA, the evaluation cores will operate for approximately 6-8 hours when running at the nominal clock frequency specified for the core.
To evaluate this core in EDK, simply:
After you purchase a license for the core, you will be able to generate a "Full" electronic license key for the latest released core version. Since the Full license key does not expire, installing it will enable you to generate new EDK systems containing the core version in question indefinitely. Systems containing the core generated with a Full license will not time out when programmed into an FPGA.
Please refer to the Master IP Release Note Guide for the latest information and Known Issues for this core.