| Summary |
| Access to the Xilinx Ethernet Statistics LogiCORE™ IP is delivered by default in Simulation Only mode to allow you to evaluate the core in your system level simulation. |
| Requirements |
- Xilinx ISE® v10.1 or higher must be installed.
- Download this from the Software Updates page if you have not already done so.
- You must be registered on Xilinx.com to access this service pack.
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| License Terms |
| Please note that the conditions of the Core Evaluation License Agreement apply toward your evaluation of this core. |
| Accessing Evaluation Files |
| Simulation Only Evaluation |
Simulation Only Evaluation allows you to customize the core through a CORE Generator™ customization GUI and generate a UniSim gate level model for functional simulation. To perform a Simulation Only Evaluation:
- Make sure you have satisfied the requirements listed at the top of this page.
- Download the ISE v10.1 from the Software Updates page
- You must be registered on Xilinx.com to perform this download.
- If you have not registered, you will be given the opportunity to do so when you click to download the updates.
- Follow the Installation Instructions in the
 Getting Started Guide for this product.
- Start up the CORE Generator using either of the following two methods:
- From ISE: Select Projects -> New Source -> IP (Coregen and Architecture Wizard)
- From Windows: Select Programs -> Xilinx -> Accessories -> CORE Generator
- To access the core, double click on the "Communication & Networking" folder in the left hand panel of the CORE Generator GUI, then double click on the "Ethernet" folder.
- Double click on the Estats core to call up the IP customization GUI.
Refer to the Example Design Quick Start chapter of the Getting Started Guide for instructions on evaluating the core. |
| Full
System Hardware Evaluation |
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Since the Xilinx Estats standalone core is provided free of charge to all licensed Xilinx ISE customers, there is no "Full System Hardware Evaluation" version of this core.
Please register to download the full release core here. |
| Learn More |
| You can learn more about the Xilinx Estats LogiCORE by visiting the Ethernet Statistics product page. |
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