Xilinx provides two ways to evaluate the Endpoint PIPE for PCI Express® (PCIe®) LogiCORE™ IP: Simulation Only, and Full System Hardware Evaluation.

• Simulation Evaluation allows you to customize the core through a CORE Generator™ customization GUI and generate a Unisim-based model for functional simulation.
• Full System Hardware Evaluation allows you to do everything you can do with the Fully Licensed IP core, including configure place and route, simulate, estimate timing and program a Xilinx FPGA device.

Install these updates if you have not already done so:

(NOTE: You must be registered on Xilinx.com to access these updates.)

To perform a Simulation Only Evaluation:

1. Make sure you have installed the required software as specified in the requirements section to ensure that you have the required software and IP core version. The Simulation Eval license key is shipped with the core by default.
2. Follow the general instructions below on Generating the Core.
3. Integrate the core into your design and perform a functional simulation. See the Getting Started Guide for more details.

To perform a Full System Hardware Evaluation:

1. Make sure you have satisfied the requirements.
2. Generate a Full System Hardware Evaluation license Key.
   • The license will be generated and emailed to you automatically. Install the license as directed by the email instructions.
3. Follow the general instructions below on Generating the Core.
4. To familiarize yourself with the ISE design flow,
• Process the Example Design delivered with the core through ISE following the Quick Start instructions in the Getting Started Guide
5. To perform an in-depth evaluation in hardware in your own design:
• Instantiate the core in your own design, place and route the design using ISE, then generate a bitstream and use it to program an appropriate FPGA device.

• Start the CORE Generator using either of the following methods:
  • From ISE: Select Projects -> New Source -> IP (Coregen and Architecture Wizard)
  • From Windows: Select Programs -> Xilinx -> Accessories -> CORE Generator
• The Endpoint PIPE for PCI Express core is located in the Standard Bus Interfaces folder in the IP catalog section of the CORE Generator window.

Refer to the Example Design Quick Start chapter of the Getting Started Guide for more detailed instructions on evaluating the core.

You can learn more about the Xilinx Endpoint PIPE for PCI Express by visiting the Endpoint PIPE for PCI Express product page.

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