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SPI-4.2 IP Core Evaluation

Xilinx provides two ways to evaluate this LogiCORE™ IP core: Simulation Only, and Full System Hardware Evaluation.

  • Simulation Only Evaluation allows you to customize the core through a CORE Generator™ customization GUI and generate a UNISIM library-based structural model for functional simulation.
  • A Full System Hardware Evaluation version of the core allows you to do everything you can do with the Fully Licensed IP core, including configure place and route, simulate, estimate timing and program a Xilinx FPGA device.
Requirements

Please refer to the SPI-4.2 Solutions Offerings and System Requirements for details on core versions and System Requirements.

License Terms

Please note that the conditions of the Core Evaluation License Agreement apply toward your evaluation of this core.

Accessing Evaluation Files
Simulation Only Evaluation

To perform a Simulation Only Evaluation:

Full System Hardware Evaluation

To perform a Full System Hardware Evaluation: The procedures are the same as for the Simulation Only Evaluation, except that you must additionally request and install a Full System Hardware Evaluation license key. This will allow you to generate a bitstream that you can use to program a Xilinx FPGA and evaluate the core in hardware for a limited amount of time.

  1. Make sure you have satisfied the Requirements.
  2. Generate a Full System Hardware Evaluation License Key.
    • The license will be generated and emailed to you automatically. Install the license as directed by the email instructions.
  3. Follow the general instructions below to load the CORE Generator IP customization GUI for this core and generate the core.
  4. For some cores, an Example Design is written to your project directory by CORE Generator system when you generate the core. If an example design is provided, instructions will be documented in a Getting Started Guide or User Guide document.
  5. To perform an in-depth evaluation in hardware in your own design:
    • Instantiate the core in your own design, place and route the design using ISE, then generate a bitstream and use it to program an appropriate FPGA device.
Note

The evaluation core will cease to function in a programmed FPGA device after a period of time. See the Requirements page for this core for information on the duration of this time period.

General Instructions
  • Start up the CORE Generator using either of the following two methods:
    • From ISE®: Select Projects -> New Source -> IP (Coregen and Architecture Wizard)
    • From Windows: Select Programs -> Xilinx ISE -> Accessories -> CORE Generator
  • Locate your core the IP catalog section of the CORE Generator window.
    • Double click on the core to call up the customization GUI, select your desired parameters, and click the "Finish" button to generate the core.

 

Release Notes & Known Issues

Please refer to the Master IP Release Note Guide for the latest information and Known Issues for this core.

 
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