This page contains information on how to evaluate the various soft Tri-Mode Ethernet MAC cores delivered in Vivado® IDE and EDK.
While the soft TEMAC cores require purchase of a separate license, the HDL Wrappers and cores supporting the hard TEMAC blocks embedded in the fabric of Virtex®-4 FX and Virtex-5 LXT/SXT devices are delivered with full access in ISE or EDK at no additional cost.
Standalone soft Tri-Mode Ethernet MAC (Vivado® IDE)
Xilinx provides two ways to evaluate the standalone soft Tri-Mode Ethernet MAC (TEMAC) Core: Simulation Only and Full System Hardware Evaluation.
- Simulation Only Evaluation allows you to customize the core through the Vivado® IDE.
- A Full System Hardware Evaluation version of the TEMAC core allows you to do everything you can do with the fully licensed IP core, including configure, place and route, simulate, estimate timing and program a Xilinx FPGA device.
Please note that the conditions of the Core Evaluation License Agreement apply toward your evaluation of this core.
To perform a Simulation Only Evaluation:
XPS_LL_TEMAC (soft TEMAC configuration)
Standalone soft TEMAC core
The evaluation core will cease to function in a programmed FPGA device after a period of time. See the Requirements page for this core for information on the duration of this time period.
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:
For details, see the sections, “Working with IP” and “Customizing IP for the Design” in the Vivado Design Suite User Guide: Designing with IP (UG896) and the “Working with the Vivado IDE” section in the Vivado Design Suite User Guide: Getting Started (UG910).
For information on New Features, Known Issues, and Patches please refer to the Installation, Licensing and release Notes document available on this page: http://www.xilinx.com/support/licensing_solution_center.htm