Soft Tri-mode Ethernet MAC IP Core Evaluation

This page contains information on how to evaluate the various soft Tri-Mode Ethernet MAC cores delivered in ISE® CORE Generator™ and EDK™.

While the soft TEMAC cores require purchase of a separate license, the HDL Wrappers and cores supporting the hard TEMAC blocks embedded in the fabric of Virtex®-4 FX and Virtex-5 LXT/SXT devices are delivered with full access in ISE or EDK at no additional cost.


Please refer to the Requirements link on the product page for this core for details on System Requirements.

Soft TEMAC Offerings

Standalone soft Tri-Mode Ethernet MAC (ISE CORE Generator)

Xilinx provides two ways to evaluate the standalone soft Tri-Mode Ethernet MAC (TEMAC) Core: Simulation Only and Full System Hardware Evaluation.

  • Simulation Only Evaluation allows you to customize the core through a CORE Generator customization GUI and generate a SimPrim-based gate level model for functional simulation.

  • A Full System Hardware Evaluation version of the TEMAC core allows you to do everything you can do with the fully licensed IP core, including configure place and route, simulate, estimate timing and program a Xilinx FPGA device.


  • Xilinx supports Full System Hardware Evaluation of the soft TEMAC configuration of the XPS_LL_TEMAC core in EDK.
License Terms

Please note that the conditions of the Core Evaluation License Agreement apply toward your evaluation of this core.

Accessing Evaluation Files
Simulation Only Evaluation

To perform a Simulation Only Evaluation:

Full System Hardware Evaluation

XPS_LL_TEMAC (soft TEMAC configuration)

  1. Make sure you have satisfied the requirements.
  2. Follow the instructions on the Processor IP Evaluation page to perform a Full System Hardware Evaluation of the soft TEMAC configuration of the XPS_LL_TEMAC core.

Standalone soft TEMAC core

  1. Make sure you have satisfied the Requirements.
  2. Generate a Full System Hardware Evaluation License Key.
    • The license will be generated and emailed to you automatically. Install the license as directed by the email instructions.
  3. Follow the general instructions below to load the CORE Generator IP customization GUI for this core and generate the core.
  4. For some cores, an Example Design is written to your project directory by CORE Generator system when you generate the core. If an example design is provided, instructions will be documented in a Getting Started Guide or User Guide document.
  5. To perform an in-depth evaluation in hardware in your own design:
    • Instantiate the core in your own design, place and route the design using ISE, then generate a bitstream and use it to program an appropriate FPGA device.

The evaluation core will cease to function in a programmed FPGA device after a period of time. See the Requirements page for this core for information on the duration of this time period.

General Instructions
  • Start up the CORE Generator using either of the following two methods:
    • From ISE®: Select Projects -> New Source -> IP (Coregen and Architecture Wizard)
    • From Windows: Select Programs -> Xilinx ISE -> Accessories -> CORE Generator
  • Locate your core the IP catalog section of the CORE Generator window.
    • Double click on the core to call up the customization GUI, select your desired parameters, and click the "Finish" button to generate the core.


Release Notes & Known Issues

Please refer to the Master IP Release Note Guide for the latest information and Known Issues for this core.