| Summary |
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Xilinx provides two ways to evaluate the VLYNQ Core: Simulation Only, and Full System Hardware Evaluation.
- Simulation Only Evaluation allows you to customize the core through a CORE Generator software customization GUI and generate a Unisim-based model for functional simulation.
- Full System Hardware Evaluation allows you to do everything you can do with the Fully Licensed IP core, including configure, place and route, simulate, estimate timing and program a Xilinx® FPGA device.
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| Requirements |
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To use the VLYNQ Interface, you must install the following software:
(NOTE: You must be registered on xilinx.com to access these updates) |
| License Terms |
| The conditions of the Core
Evaluation License Agreement apply toward your evaluation
of this core. |
| Accessing the Evaluation Files |
| Simulation
Only Evaluation |
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To perform a Simulation Only Evaluation:
- Make sure you have installed the required software as
specified in the requirements section to ensure that you
have the required software and IP core version. The Simulation
Eval license key is shipped with the core by default.
- Follow the general instructions below on Generating
the Core.
- Integrate the core into your design and perform a functional
simulation. See the
Getting
Started Guide for more details.
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| Full System Hardware Evaluation |
| To perform a Full System Hardware Evaluation:
- Make sure you have satisfied the requirements.
- Generate
a Full System Hardware Evaluation license Key.
- The license will be generated and emailed to you automatically.
Install the license as directed by the email instructions.
- Follow the general instructions below on Generating
the Core.
- To familiarize yourself with the ISE design flow,
- Process the Example Design delivered with the
core through ISE following the Quick Start instructions
in the
Getting
Started Guide .
- To perform an in-depth evaluation in hardware in your
own design:
- Instantiate the core in your own design, place and route
the design using ISE, then generate a bitstream and use
it to program an appropriate FPGA device.
| Note that the core will cease to function in the programmed
device after 2 - 8 hours. |
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| Generating
the Core |
- Start the CORE Generator using either of the following
methods:
- From ISE: Select Projects -> New Source
-> IP (Coregen and Architecture Wizard)
- From Windows: Select Programs -> Xilinx
-> Accessories -> CORE Generator
- The VLYNQ core is located in the Telecommunications folder under Communications & Networking in the IP catalog section of the CORE
Generator window.
Refer to the Example Design Quick Start chapter of the
Getting
Started Guide for more detailed instructions on evaluating
the core.
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| Release Notes & Known Issues |
| Please review the Master Release Notes Guide for Xilinx IP Cores |
| Learn More |
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You can learn more about the Xilinx VLYNQ LogiCORE™ IP core by visiting the product page.
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