| LogiCORE™ | Version | Software Requirements | AXI Support | Supported Device Families |
|---|---|---|---|---|
| 3GPP LTE UL Channel Decoder
|
v4.0
v3.0 |
Vivado™ 2013.1
ISE® 14.1
|
AXI4 AXI4-Stream |
Zynq™-7000 Artix™-7 Kintex™-7 / -2L Virtex®-7 / -2L / XT Zynq-7000 Artix-7 Kintex-7 / -2L Virtex-7 / -2L / XT Virtex-6 CXT / HXT / LXT / SXT / -1L Virtex-5 LX / LXT / SXT / TXT / FXT Spartan®-6 LX / LXT |
| 3GPP LTE DL Channel Encoder
|
v3.0
v2.2 |
Vivado 2012.2
ISE 14.1
|
AXI4-Stream | Zynq-7000 Artix-7 Kintex-7 Virtex-7 Zynq-7000 Artix-7 Kintex-7 / -2L Virtex-7 / -2L / XT Virtex-6 CXT / HXT / LXT / SXT Virtex-5 TXT / FXT / SXT / LXT Virtex-5 LX Spartan-6 LX / LXT |
Download the required software from the Xilinx.com Downloads page.
Check the IP Release Notes Guide for information on any required patches.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for approximately 2-3 hours. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again