Hardware Evaluation Time Out Period
A Hardware Evaluation license for the above LogiCORE IP cores will enable you to parameterize, generate and instantiate this cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores will be fully functional in the programmed device for approximately 2 - 3 hours. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again |