Xilinx provides fully configurable LogiCORE solutions for the System Packet Interface Level 3 (SPI-3) interface. The cores are designed to work with the latest Virtex and Spartan FPGAs and are smoothly implement into the Xilinx design flow.

The SPI-3 interface cores support OC-48 2.4 Gbps data rates and are used in Gb routers, terabit switches, optical cross connect switches, and a wide range of multi-service DWDM and SONET/SDH based transmission system transport technologies.

The cores address the increasing demands of network Internet Protocol (IP) traffic by ensuring cores are compliant with the Optical Internetworking Forum's (OIF) SPI-3 standard, also known as SATURN® Development Group's POS-PHY™ Level 3 (PL3) interface.

Please contact your local Xilinx Sales Office for additional details.

The Basics of SPI-3

Packet Over SONET/SDH (POS) enables network core routers to send native IP packets directly over SONET/SDH frames. POS provides lower packet overhead and lower cost per Mbit than any other data transport method. These efficiencies, along with the increasing evolution of the optical network, enable POS to efficiently support increases in IP traffic over existing and new fiber networks.

The Packet Over SONET Physical Layer Level 3 (POS-PHY L3) interface defines the interconnection of Physical Layer devices to Link Layer devices in POS applications. The interface cores, referred to as SPI-3 cores, perform the interface functions on the Physical Layer or Link Layer side of the interface.

Product Strategy

The Xilinx POS-PHY strategy is to develop complementary cores that interoperate with leading ASSP developers. The cores are developed in collaboration with the industry leaders (Intel, PMC-Sierra, and other industry leaders) and verified together with Xilinx engineers on reference designs.