SPI-4.2 Interoperability

Proven Interoperability Between PMC-Sierra, Mindspeed and Xilinx SPI-4.2 (PL4) Cores

PMC-Sierra and SPI-4.2 Core HW Interoperability

PMC-Sierra's XENON family of devices and Xilinx Virtex™ family FPGA based SPI-4.2/PL4 cores have proven hardware interoperability for both static and dynamic alignment modes. This proven interoperability allows system architects to focus on system level aspects of the design rather than verifying connectivity. As such, the interoperability will help accelerate the development of emerging Metro Area Network (MAN) equipment such as multi-service routers and switches with support for 10 Gigabit Ethernet, High Density Gigabit Ethernet, OC-192, 4 x OC-48 POS/ATM.

Mindspeed and SPI-4.2 Core HW Interoperability

Mindspeed's OptiPHY-F10G OC-192 and Xilinx Virtex family FPGA based SPI-4.2/PL4 cores have proven hardware interoperability for static alignment modes. As a result, customers have a seamless solution for designing an OC-192 Packet-over-SONET application.

The OptiPHY-F10G is the first SONET framer with an embedded SPI-4.2 interface to be tested at full speed with a SPI-4.2 core in the Virtex family FPGA. The SPI-4.2 interface ensures a low-power and low-pin-count interface enabling significantly easier, less expensive integration of next-generation equipment designs.