The Basics of POS-PHY L4

Packet Over SONET/SDH (POS) enables network core routers to send native IP packets directly over SONET/SDH frames. POS provides lower packet overhead and lower cost per Mbit than any other data transport method. These efficiencies, along with the increasing evolution of the optical network, enable POS to efficiently support increases in IP traffic over existing and new fiber networks. 

The Packet Over SONET Physical Layer Level 4 (POS-PHY L4) interface defines the interconnection of Physical Layer devices to Link Layer devices in POS applications. The interface cores, referred to as SPI-4.2 cores, make use of unique features available in the Virtex™-5, Virtex-4, and Virtex-II series of FPGAs. These features include the Digital Clock Manager (DCM), enhanced Block RAM, and high-speed LVDS I/O buffers in conjunction with double data rate (DDR) registers and embedded SERDES to support data rates in excess of 1-Gbps per pin pair.

Product Summary

Xilinx provides fully configurable netlist LogiCORE solutions for the SPI-4.2 interface. The cores are designed to work with the latest Virtex-5, Virtex-4, Virtex-II Pro, Virtex-II, and Spartan™-3 FPGAs and are smoothly implemented into the Xilinx design flow.  

The interface cores support OC-192 10 Gbps data rates and are used in Gb routers, terabit switches, optical cross connect switches, and a wide range of multi-service DWDM and SONET/SDH based transmission system transport technologies. 

The cores address the increasing demands of network Internet Protocol (IP) traffic by ensuring cores are compliant with the Optical Internetworking Forum's (OIF) SPI-4 Phase 2 standard also known as SATURN® Development Group's POS-PHY™ Level 4 (PL4) interface.

The core is also available in a size/cost optimized "Lite" configuration, supporting OC-48 and 2x OC-48 applications, exceeding 5-Gbps data rates. Please contact your local Xilinx Sales Office for additional details.

Product Strategy