CoreConnect is an IBM-developed on-chip bus-communications link that enables chip cores from multiple sources to be interconnected to create entire new chips.
Processor Local Bus (PLB)
The PowerPC® 440 AND 405 core accesses high speed and high performance system resources through Processor Local Bus (PLBV46) interfaces on the instruction and data cache controllers.
- The PLB interfaces provide separate 32-bit address and 128-bit data buses for the instruction and data sides.
- The PLB supports read and write data transfers between master and slave devices equipped with a PLB bus interface and connected through PLB signals.
- Fully synchronous bus architecture supports multiple master and slave devices. Each PLB master is attached to the PLB through separate address, read-data, and write-data buses.
- PLB slaves are attached to the PLB through shared, but decoupled, address, read-data, and write-data buses and a plurality of transfer control and status signals for each data bus.
- An arbitration locking mechanism is provided to support master-driven atomic operations.
- PLB arbiters can be implemented on the FPGA fabric and are available as soft IP cores.
- Timing for all PLB signals is provided by a single clock source that is shared by all masters and slaves attached to the PLB.
- Supports Virtex™-5, Virtex-4, and Virtex-II Pro family devices.
On-chip Peripheral Bus (OPB)
The PowerPC 405 core accesses low speed and low performance system resources through On-chip Peripheral Bus (OPB).
- Fully synchronous bus that functions independently at a separate level of bus hierarchy. It is not intended to connect directly to the processor core.
- Interfaces provide separate 32-bit address and up to 32-bit data buses.
- Supports multiple master devices, the address bus and data bus are implemented as a distributed multiplexer.
- Can access the slave peripherals on this bus through the "PLB to OPB" bridge unit. Peripherals which are OPB bus masters can access memory on the PLB through the "OPB to PLB" bridge unit.
- OPB arbiters can be implemented on FPGA fabric and are available as soft IP cores.
- Supports Virtex-4 and Virtex-II Pro family devices.
Device Control Register Bus (DCR)
The Device Control Register (DCR) bus is designed to transfer data between the CPU's general purpose registers (GPRs) and the DCR slave logic's device control registers (DCRs).
- Removes configuration registers from the memory address map, which reduces loading and improves bandwidth of the PLB.
- Fully synchronous bus provides 10-bit address bus and 32-bit data bus.
- Typically implemented as a distributed mux across the chip. The implementation is such that each sub-unit not only has a path to place its own DCRs on the CPU's DCR read path, but also has a path which bypasses its DCRs and places another unit's DCRs on the CPU's DCR read path.
- Privileged for both read and write.
- Supports Virtex-5, Virtex-4, and Virtex-II Pro family devices.