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Xilinx Processor IP Sizing Calculator

The Processor IP calculator is an online tool to help you easily
estimate the Processor IP core size usage in Virtex™-II Pro
devices.

Step 1: Select the Processor IP core you plan to use in your
processor system. Some cores offer min and max values based
on no options selected for core or all options selected for core,
respectively. Some cores also offer the ability to select multiple instances of the core.

Step 2: At the bottom of the tool, click on "Calculate Total Logic
Cell Count" to determine the approximate number of LUTs in
your processor system and the target Virtex-II Pro FPGA.

	MIN	MAX
MicroBlaze™ Soft Processor
None
Infrastructure IP Cores
OPB Arbiter & Bus Structure, 2M x 2S	MIN	MAX
OPB Arbiter & Bus Structure, 4M x 4S	MIN	MAX
OPB Arbiter & Bus Structure, 8M x 8S	MIN	MAX
None
PLB Arbiter & Bus Structure, 2M x 2S
PLB Arbiter & Bus Structure w/ DCR Interface, 2M x 2S
PLB Arbiter & Bus Structure, 4M x 4S
PLB Arbiter & Bus Structure w/ DCR Interface, 4M x 4S
PLB Arbiter & Bus Structure, 8M x 8S
PLB Arbiter & Bus Structure w/ DCR Interface, 8M x 8S
None
OPB2OPB Bridge Lite
None
OPB2PLB Bridge	MIN	MAX
None
PLB2OPB Bridge
None
DCR, 2S
DCR, 4S
DCR, 8S
DCR, 16S
None
OPB2DCR Bridge	MIN	MAX
None
OPB2PCI Full Bridge (32/33), No DMA
OPB2PCI Full Bridge (32/33), w/ DMA
None
Memory IP Cores
OPB EMC (Flash, SRAM, and ZBT), 1 Mem Device
OPB EMC (Flash, SRAM, and ZBT), 4 Mem Device
OPB EMC (Flash, SRAM, and ZBT), 8 Mem Device
None
OPB EMC (Flash, SRAM, and ZBT), 8-Bit Data Width
OPB EMC (Flash, SRAM, and ZBT), 16-Bit Data Width
OPB EMC (Flash, SRAM, and ZBT), 32-Bit Data Width
None
PLB EMC (Flash, SRAM, and ZBT), 1 Mem Device
PLB EMC (Flash, SRAM, and ZBT), 4 Mem Device
PLB EMC (Flash, SRAM, and ZBT), 8 Mem Device
None
PLB EMC (Flash, SRAM, and ZBT), 8-Bit Data Width
PLB EMC (Flash, SRAM, and ZBT), 8-Bit Data Width w/ Burst and Cacheline Transfers
PLB EMC (Flash, SRAM, and ZBT), 16-Bit Data Width
PLB EMC (Flash, SRAM, and ZBT), 16-Bit Data Width w/ Burst and Cacheline Transfers
PLB EMC (Flash, SRAM, and ZBT), 32-Bit Data Width
PLB EMC (Flash, SRAM, and ZBT), 32-Bit Data Width w/ Burst and Cacheline Transfers
PLB EMC (Flash, SRAM, and ZBT), 64-Bit Data Width
PLB EMC (Flash, SRAM, and ZBT), 64-Bit Data Width w/ Burst and Cacheline Transfers
None
OPB BRAM Controller
None
PLB BRAM Controller
None
OPB DDR Controller
None
PLB DDR Controller
PLB DDR Controller w/ Burst and Cacheline Transfers
None
OPB SDRAM Controller, 8-Bit Data Width
OPB SDRAM Controller, 16-Bit Data Width
OPB SDRAM Controller, 32-Bit Data Width
None
PLB SDRAM Controller, 8-Bit Data Width
PLB SDRAM Controller, 16-Bit Data Width
PLB SDRAM Controller, 32-Bit Data Width
None
Peripheral IP Cores
OPB 10/100 Ethernet MAC ($), Minimal IPIF
OPB 10/100 Ethernet MAC ($$), IPIF, No DMA
OPB 10/100 Ethernet MAC ($), IPIF w/ Simple DMA
OPB 10/100 Ethernet MAC ($), IPIF w/ SG DMA
None
OPB 10/100 Ethernet MAC Lite ($), Full Duplex
OPB 10/100 Ethernet MAC Lite ($), Half Duplex
None
OPB ATM Utopia Level 2 Slave ($), Minimal IPIF
OPB ATM Utopia Level 2 Slave ($), IPIF, No DMA
OPB ATM Utopia Level 2 Slave ($), IPIF w/ Simple DMA
OPB ATM Utopia Level 2 Slave ($), IPIF w/ SG DMA
None
OPB ATM Utopia Level 2 Master ($), Minimal IPIF
OPB ATM Utopia Level 2 Master ($), IPIF, No DMA
OPB ATM Utopia Level 2 Master ($), IPIF w/ Simple DMA
OPB ATM Utopia Level 2 Master ($), IPIF w/ SG DMA
None
OPB Single Channel HDLC ($), IPIF, No DMA
OPB Single Channel HDLC ($), IPIF w/ Simple DMA
OPB Single Channel HDLC ($), IPIF w/ SG DMA
None
1 2 3 4 5 6 OPB I2C Master & Slave ($)
None
1 2 3 4 5 6 OPB SPI Master & Slave, w/o Rx & Tx FIFOs
1 2 3 4 5 6 OPB SPI Master & Slave, w/ Rx & Tx FIFOs
None
OPB Interrupt Controller, 2 Interrupts	MIN	MAX
OPB Interrupt Controller, 4 Interrupts	MIN	MAX
OPB Interrupt Controller, 8 Interrupts	MIN	MAX
OPB Interrupt Controller, 16 Interrupts	MIN	MAX
OPB Interrupt Controller, 32 Interrupts	MIN	MAX
None
DCR Interrupt Controller, 2 Interrupts
DCR Interrupt Controller, 4 Interrupts
DCR Interrupt Controller, 8 Interrupts
DCR Interrupt Controller, 16 Interrupts
DCR Interrupt Controller, 32 Interrupts
None
1 2 3 4 5 6 OPB UART 16450 ($)
None
1 2 3 4 5 6 OPB UART 16550 ($)
None
1 2 3 4 5 6 OPB UART Lite	MIN
1 2 3 4 5 6 OPB UART Lite	MAX
None
OPB UART JTAG	MIN	MAX
None
1 2 3 4 5 6 OPB Timebase / WDT
None
1 2 3 4 5 6 OPB Timer / Counter
None
1 2 3 4 5 6 OPB GPIO, 1 I/O
1 2 3 4 5 6 OPB GPIO, 8 I/Os
1 2 3 4 5 6 OPB GPIO, 16 I/Os
1 2 3 4 5 6 OPB GPIO, 32 I/Os
None
Optional IPIF Modules For Your Customized Logic
OPB IPIF-Slave Attachment, S Only w/o Burst
OPB IPIF-Slave Attachment, S Only w/ Burst
OPB IPIF-Slave Attachment, M & S w/ Burst
None
OPB IPIF-Master Attachment, Single M
OPB IPIF-Master Attachment, Dual M Arbitration
None
PLB IPIF-Slave Attachment, S only w/o Burst
PLB IPIF-Slave Attachment, S only w/ Burst and Address Decode
PLB IPIF-Slave Attachment, M & S w/ Burst
None
PLB IPIF-Master Attachment, Single M
PLB IPIF-Master Attachment, Dual M Arbitration
None
IPIF Address Decode, SRAM Decode
IPIF Address Decode, 1 Reg Decode
IPIF Address Decode, 8 Reg Decode
IPIF Address Decode, 32 Reg Decode
None
IPIF Interrupt Control, 1 Interrupt	MIN	MAX
IPIF Interrupt Control, 4 Interrupt	MIN	MAX
IPIF Interrupt Control, 8 Interrupt	MIN	MAX
IPIF Interrupt Control, 16 Interrupt	MIN	MAX
None
IPIF Read Packet FIFO, 4 x 16	MIN	MAX
IPIF Read Packet FIFO, 32 x 512	MIN	MAX
IPIF Read Packet FIFO, 64 x 16K	MIN	MAX
None
IPIF Write Packet FIFO, 4 x 16	MIN	MAX
IPIF Write Packet FIFO, 32 x 512	MIN	MAX
IPIF Write Packet FIFO, 64 x 16K	MIN	MAX
None
IPIF DMA, 1 Channel
IPIF DMA, 2 Channels
None
IPIF Scatter Gather, 1 Channel
IPIF Scatter Gather, 2 Channels
None

IP Cores Calculator
Targeted Device: