Fully compliant with v1.3 of the RapidIO Interconnect Specification

Product Summary

The LogiCORE™ RapidIO Physical Layer, a fixed netlist solution for the RapidIO interconnect, is a pre-implemented and fully tested module for Xilinx Virtex™-II series FPGAs. The pinout for the device and the relative placement of the internal logic are pre-defined. Critical paths are controlled by a constraints file which ensures predictable timing thereby significantly reducing engineering time required to implement the RapidIO Physical Layer portion of a design; resources can be focused on unique user application logic in the FPGA and on the system-level design. As a result, the LogiCORE RapidIO Physical Layer products can minimize your product development time. Xilinx Virtex-II  and Virtex-II Pro series FPGAs enable designs of fully RapidIO compliant systems.

Serial 1x & 4x Physical Layer  Key Features 

• Available under terms of the SignOnce IP License
• Fully compliant with RapidIO Interconnect Specification V1.3
  • Supports 1 and 4 lane operating with 64-bit internal data path
• Uses Virtex-II Pro Multi-Gigabit Transceivers to achieve high transceiver capability
• Supports 1.25, 2.5 and 3.125 Gbps line speed
• Supports 1 lane operating with 64-bit internal data path
• Elastic buffers and clock compensation
• Automatic clock data recovery
• 8b/10b encode/decode
• Supports packet retry, stomp, transmission error recover, throttle-based flow control, multi-cast event, and CRC
• Separate clock domain to control management interface for reading and writing configuration registers
• Standardized user interface with LocalLink
• Easy-to-use packet-based interface
• Full-duplex communication
• Back-to-back transactions enable greater link bandwidth utilization
• Supports flow control of data and discontinuatin of an in-process packet in the transmit and receive direction
• Flexible buffer management scheme
• Supports removal or corrupted packts for error detection and initiates automatic error recovery
• Design verified using the RapidIO Trade Association Bus Functional Model
• Complete set of documentation

LVDS Physical Layer Key Features 

• The FPGA devices meet all required electrical and timing parameters including AC output drive characteristics, setup, hold, and clock to output as stated in the 250MHz RapidIO AC specification v1.3
• Pre-implemented module for Virtex-II & Virtex-II Pro FPGAs 
• 8-bit LVDS port with 64-bit internal data path
• 250 MHz clock rate, 500Mbps per LVDS pin pair
• Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
• Dynamic clock phasing alignment 
• Flexible buffer management scheme
• Reduced product development time 
• Predefined device pinout and relative placement of internal logic
• Critical paths are controlled by a constraints file ensuring predictable timing
• Companion testbench