Product Summary

The RapidIO Logical and Transport Layer is pre-implemented and fully tested module that is optimized for Xilinx Virtex™-5 LXT/SXT, Virtex-4 FX and Virtex-II/Pro series FPGAs. Critical paths are controlled by a constraints file that ensures predictable timing and significantly reduces the engineering time required to implement the Logical (I/O) and Transport Layer portion of a design. Resources can instead be focused on unique user application logical in the FPGA and on the system level design. As a result, the Xilinx RapidIO Logical (I/O) and Transport products can minimize your product development time. 

Xilinx Virtex-5 LXT/SXT, Virtex-4 FX and Virtex-II/Pro series FPGAs enable designs of fully RapidIO complaint systems. The design is carefully optimized for best possible performance and utilization in Virtex-5 LXT/SXT, Virtex-4 FX and Virtex-II series and Virtex-II Pro FPGA devices. 

Drawing on the architectural advantages of Xilinx FPGAs, Xilinx Smart-IP technology ensures highest performance, predictability, repeatability, and flexibility in RapidIO designs. The Smart-IP technology is incorporated in every RapidIO interface. Xilinx Smart-IP technology leverages the Xilinx architecture advantages such as look-up tables, block RAM, Digital Clock Manager and segmented routing. This technology provides the best physical layout, predictability, and performance. Additionally, these features allow for significantly reduced compile times over competing architectures. The Logical (I/O) and Transport Layer has been tested to meet timing in the supported devices of the Virtex-5 LXT/SXT, Virtex-4 FX and Virtex-II and Virtex-II Pro series FPGAs. You can contact Xilinx Design Services or one of the Xilinx XPERT partners for additional features and devices/packages support.

Key Features

• Implements Rev 1.3 of the RapidIO Input/Output Logical and Common Transport Layer Specification
• Supports concurrent Initiator and Target operations
• 64-bit data path
• Dedicated port for Maintenance transactions
• Six separate User ports with independent data flow control, includes two Maintenance ports that can interface with the Xilinx Register Manager or a User defined module. The User ports include:
• Initiator Request (Ireq) Port: Handles outgoing requests
• Initiator Response (Iresp) Port: Handles incoming responses
• Target Request (Treq) Port: Handles incoming requests
• Target Response (Tresp) Port: Handles outgoing responses
• Maintenance Port: Handles maintenance requests (Mreq) and maintenance responses (Mresp)
• Configuration Register Port: Interfaces to the configuration register space (CAR/CSRs)
• Supports an aggregate throughput of 10 Gb/s (optimal buffer design is needed to meet this throughput)
• Simple handshaking mechanism to control data flow