To seccessfully integratae the functional simulation models with your design simulation, the following system requirements must be met:
| LogiCORE™ | Version | AXI Support | Software Requirements | Supported Device Families |
|---|---|---|---|---|
| Serial RapidIO IP Gen 2
|
v2.0
v1.6 |
AXI4-Stream AXI4-Lite |
Vivado™ 2013.1
ISE® 14.4
|
Zynq™-7000** Artix™-7 Kintex™-7 / -2L Virtex®-7 / -2L / XT Artix-7 Kintex-7 / -2L Virtex®-7 / -2L / XT / HT Virtex-6 HXT / LXT / SXT / CXT |
| RapidIO Physical Layer Interface Core
Gen 1
|
v5.6 | ISE 13.1
|
Virtex-6 HXT / LXT / SXT Virtex-5 FXT / SXT / LXT Virtex-4 FX
Spartan®-6 LXT |
|
| RapidIO Logical (I/O) and Transport Layer Interface Core
Gen 1
|
v5.6 | ISE 13.1
|
Virtex-6 HXT / LXT / SXT Virtex-5 FXT / SXT / LXT Virtex-4 FX
Spartan-6 LXT |
**Early Access. Contact your Xilinx FAE to request the required license key.
Download the required software from the Xilinx.com Downloads page.
Check the IP Release Notes Guide for information on any required patches.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for approximately 8 hours. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again