SPI-3 Link Layer Interface, Multi-channel LogiCORE IP Offerings & System Requirements
| This page lists the core configurations included with your purchase of the Xilinx SPI-3 Link Layer Interface, Multi-channel LogiCORE™ IP product, along with detailed information on System Requirements. | ||||
| System Requirements | ||||
| LogiCORE | Version | Software Support | Supported Devices | |
|
SPI-3 Link Layer Interface, Multi-channel |
v6.1 |
ISE® 11.3 ISE IP Update 11.3 |
Virtex®-6 LXT / SXT / HXT / -1L |
|
v5.1 |
ISE 9.2i Service Pack 2 or higher |
Virtex-II Pro Virtex-II |
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Hardware Evaluation Time Out Period A Hardware Evaluation license for the above LogiCORE IP core will enable you to parameterize, generate and instantiate this core in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware. The IP core will be fully functional in the programmed device for approximately 3 hours. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again |
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| Required Patches | Check the IP Release Notes Guide for information on any required patches. | |||
Download the software requirements from the Software Updates page if you have not already done so. |
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