Xilinx offers the following Tri-Mode Ethernet MAC solutions:

• Hard TEMAC Blocks
• Soft TEMAC Cores (licensed separately)

• The Hard TEMAC Block cores are included in either the ISE® CORE Generator™ or EDK software at no cost

Included with

ISE CORE Generator

ISE 11.3 or higher

ISE IP Update 11.3 (IP_11.3)

Virtex-6 HXT
Virtex-6 SXT
Virtex-6 LXT
Virtex-6 -1L

Included with

ISE CORE Generator

ISE 11.1 or higher

ISE IP Update 11.1 (IP_11.1)

Virtex-5 TXT
Virtex-5 FXT
Virtex-5 SXT
Virtex-5 LXT

Included with

ISE CORE Generator

ISE 11.1 or higher

ISE IP Update 11.1 (IP_11.1)

Included with EDK

PLB TEMAC

Hard Virtex-5 TEMAC configuration)

ISE 9.2i SP2
or higher

ISE 9.2i IP Update 2

EDK 9.2i
SP2 or higher

XPS_LL_TEMAC
v2.02a

(Hard TEMAC Configuration)

ISE 11.2
or higher

ISE IP Update 11.2

EDK 11.2 or higher

Virtex-4 FX
virtex-4 SX
Virtex-4 LX

• Use the soft Tri-Mode Ethernet MAC cores:
  • When targeting Spartan® family devices, or
  • To add additional TEMAC blocks to designs which require more TEMACs than what is available as hard blocks on some Xilinx FPGA family devices.

ISE 11.3 or higher

ISE IP Update 11.3 (IP_11.3)

ISE 9.2i SP2

ISE 9.2i IP Update 2

XPS_LL_TEMAC
v2.02a

(Soft TEMAC configuration)

ISE 11.2
or higher

ISE IP Update 11.2

EDK 11.2 or higher

Hardware Evaluation Time Out Period (Applies to soft cores only)

A Hardware Evaluation license for the LogiCORE™ IP core will enable you to parameterize, generate and instantiate this cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.

The IP cores will be fully functional in the programmed device for approximately 8 hours. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again