Xilinx Tri-Mode Ethernet MAC Offerings and Software Requirements

Xilinx offers the following Tri-Mode Ethernet MAC solutions:

Soft TEMAC Cores (licensed separately
Hard TEMAC Blocks

Soft TEMAC Cores Software Requirements Table

The Xilinx® Soft Tri-Mode Ethernet MAC cores must be licensed separately under either a Project or Site License.

Use the soft Tri-Mode Ethernet MAC cores:
- When targeting 7 Series devices, or
- When targeting Spartan® family devices, or
- To add additional TEMAC blocks to designs which require more TEMACs than what is available as hard blocks on some Xilinx FPGA family devices.

Hardware Evaluation Time Out Period * : ~8 hrs

LogiCORE	Delivery Tool	Software Support	Licensing	AXI4 Support	Supported Device Families
Tri-mode Ethernet MAC v5.2 (AXI)	ISE CORE Generator	ISE 13.4	Must license EF-DI-TEMAC-PROJ or EF-DI-TEMAC-SITE	AXI4-Stream AXI4-Lite	Artix™-7 Kintex™-7 / -2L Virtex®-7 / XT / -2L Virtex-6 HXT / LXT / SXT / CXT / -1L Spartan-6 LX / LXT
Tri-mode Ethernet MAC v4.5 (Non-AXI)	ISE CORE Generator	ISE 13.1	Must license EF-DI-TEMAC-PROJ or EF-DI-TEMAC-SITE		Virtex-6 HXT / LXT / SXT / -1L Virtex-5 FXT / SXT / LXT Virtex-5 LX Virtex-4 FX / SX / LX Spartan-6 LX / LXT Spartan-3A DSP Spartan-3 / 3E
Tri-mode Ethernet MAC v3.4		ISE 9.2i SP2 ISE 9.2i IP Update 2	Must license EF-DI-TEMAC-PROJ or EF-DI-TEMAC-SITE		Virtex-II Pro / Virtex-II
AXI Ethernet v3.00a	EDK	ISE 13.2	Must license EF-DI-TEMAC-PROJ, EF-DI-TEMAC-SITE, or use no charge Embedded TEMAC in Virtex Devices	AXI4-Stream AXI4-Lite	Kintex-7 Virtex-7 Virtex-6 HXT / LXT / SXT Spartan-6 LXT / LX
XPS_LL_TEMAC v2.03a (Soft TEMAC Configuration)	EDK	ISE® 12.4 EDK 12.4	Must license EF-DI-TEMAC-PROJ, EF-DI-TEMAC-SITE, or use no charge Embedded TEMAC in Virtex Devices		Virtex-5 SXT / LXT Virtex-5 LX Virtex-4 FX / SX / LX Spartan-3A / 3AN / 3A-DSP
AXI Ethernet Lite v1.01b	EDK	EDK 13.4	Included with EDK	AXI4 AXI4-Lite	Kintex-7 Artix-7 Virtex-7 Virtex-6 HXT / LXT / SXT Spartan-6 LXT / LX
XPS Ethernet Lite v4.00a	EDK	ISE 12.3	Included with EDK		Virtex-6 HXT / LXT / SXT Virtex-5 TXT / SXT / LX Virtex-4 SX / LX / FX Spartan-6 LXT / LX Spartan-3A / 3AN Spartan-3 / 3E

Hard TEMAC Blocks Software Requirements Table

LogiCORE™	Delivery Tool	Software Support	Licensing	AXI4 Support	Supported Device Families
. The Hard TEMAC Block cores are included in either the ISE® CORE Generator™ or EDK software at no cost
Included with ISE CORE Generator
Virtex®-6 Embedded TEMAC Wrapper v2.1 (AXI) v1.5 (Non-AXI)	Included with ISE CORE Generator	ISE 13.1	No License Required	AXI4-Stream AXI4-Lite	Virtex-6 CXT / HXT / LXT / SXT / -1L
Virtex-5 Embedded TEMAC Wrapper v1.7	Included with ISE CORE Generator	ISE 12.1	No License Required		Virtex-5 TXT / FXT / SXT / LXT
Virtex-4 Embedded TEMAC Wrapper v4.8	Included with ISE CORE Generator	ISE 12.1	No License Required		Virtex-4 FX
Included with EDK
XPS_LL_TEMAC v2.03a (Hard TEMAC Configuration)	Included with EDK	ISE 11.4 or later	Separate license not required		Virtex-6 CXT / HXT / LXT / SXT / -1L Virtex-5 FXT / SXT / LXT Virtex-4 FX / SX / LX

Download the required software from the Xilinx.com Downloads page.

Check the IP Release Notes Guide for information on any required patches.

* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.

The IP cores in this table will be fully functional in the programmed device for approximately 8 hours. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again

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