| System
Requirements |
| LogiCORE |
Version |
Software Requirements |
Required Patches |
Supported Device Families |
Color Correction Matrix
EF-DI-CCM-SITE |
v1.0
|
ISE® 11.1 or higher
ISE 11.1 IP |
Check the IP Release Notes Guide for information on any required patches. |
Virtex®-5
Spartan®-3A DSP
|
Color Filter Array Interpolation
EF-DI-CFA-SITE |
v1.0 |
ISE11.1 or higher
ISE 11.1 IP |
Check the IP Release Notes Guide for information on any required patches. |
|
Defective Pixel Correction
EF-DI-DEF-PIX-CORR-SITE |
|
ISE11.1 or higher
ISE 11.1 IP
|
Check the IP Release Notes Guide for information on any required patches. |
Virtex-5
Spartan-3A DSP
|
GAMMA Correction
EF-DI-GAMMA-SITE |
v1.0
|
ISE11.1 or higher
ISE 11.1 IP
|
Check the IP Release Notes Guide for information on any required patches. |
Virtex-5
Spartan-3A DSP |
Image Processing Pipeline
EF-DI-IMG-PIPE-SITE |
v1.0 |
IISE11.1 or higher
ISE 11.1 IP |
Check the IP Release Notes Guide for information on any required patches. |
Virtex-5
Spartan-3A DSP |
On-Screen Display
EF-DI-OSD-SITE |
v1.0 |
IISE11.3 or higher
ISE 11.3 IP |
Check the IP Release Notes Guide for information on any required patches. |
Virtex-6 HXT / LXT / SXT
Virtex-5
Spartan-6 LX / LXT
Spartan-3A DSP
|
Video DMA
EF-DI-VID-DMA-SITE |
v1.0 |
IISE11.3 or higher
ISE 11.3 IP |
Check the IP Release Notes Guide for information on any required patches. |
Virtex-6 HXT / LXT / SXT
Virtex-5
Spartan-6 LX / LXT
Spartan-3A DSP
|
Video Scaler
EF-DI-VID-SCALER-SITE |
v2.0 |
IISE11.3 or higher
ISE 11.3 IP |
Check the IP Release Notes Guide for information on any required patches. |
Virtex-6 HXT / LXT / SXT
Virtex-5
Spartan-6 LX / LXT
Spartan-3A DSP
|
Video Timing Controller
EF-DI-VID-TIMING-SITE |
v1.0 |
IISE11.2 or higher
ISE 11.1 IP |
Check the IP Release Notes Guide for information on any required patches. |
|
Hardware Evaluation Time Out Period: ~1 hr
A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for approximately 1 hour. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again |
Download the software requirements from the Software Updates page if you have not already done so. |