| Core Features - v3.0 |
| • |
Constraint lengths from 3 to 9 |
| • |
Fully parameterizable generator polynomials |
| • |
Rates from 1/2 to 1/7 |
| • |
Hard or soft inputs, soft widths 3 to 8, two input formats |
| • |
Decoding rates of 199 MSPS for a single channel and 273 MSPS for multi-channel designs |
| • |
Latency of 1 microsecond with reduced latency option |
| • |
Serial option for size vs throughput trade-off |
| • |
Speed vs Area option on parallel decoder |
| • |
Best State Calculation for lower latency and improved BER |
| • |
Multi-channel mode enables decoding of up to 32 interlaced channels with a single core |
| • |
Dual rate decoder with two rate choices, selectable in real time, with independent generator polynomials (e.g. Rate 1/2 and 1/3) |
| • |
Supports Trellis Coded Modulation |
| • |
Puncturing controlled externally by erasure pins or via fixed rate internal puncturing |
| • |
Internal fixed rate puncturing, rates 2/3 to 12/13, with parameterizable codes |
| • |
Ability to change code rate on the fly through erasure pins for any decoder rate |
| • |
Built-in BER monitor |
| • |
System Generator for DSP model |
| • |
VHDL simulation model |
| • |
Supports most standards, including CDMA2000, UMTS, IEEE-802, DVB etc. |
| • |
Free full system hardware evaluation version available online |
| • |
Compatible Encoder core available in Xilinx CORE Generator |
| • |
Downloadable over the Internet, providing instant access to the latest releases |
| • |
Incorporates Xilinx Smart-IP Technology for maximum performance |
