Viterbi Decoder LogiCORE IP Offerings & System Requirements
| This page lists the core configurations included with your purchase of the Xilinx Viterbi Decoder LogiCORE™ IP products, along with detailed information on System Requirements. | ||||
| System Requirements | ||||
| LogiCORE | Version | Software Support | Supported Devices | |
|
Viterbi Decoder |
v7.0 |
ISE®11.2 ISE IP Update 11.2 (IP_11.2) |
Virtex®-6 LXT / SXT Spartan®-6 LX / LXT |
|
v6.2 |
ISE 9.2i SP2 ISE 9.2i IP Update 2 |
Virtex-II / Virtex-II Pro Spartan-IIE / Spartan-II |
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Hardware Evaluation Time Out Period A Hardware Evaluation license for the Viterbi Decoder LogiCORE™ IP core will enable you to parameterize, generate and instantiate this cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware. The IP cores will be fully functional in the programmed device for approximately 2 - 3 hours. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again |
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| Download the software requirements from the Software Updates page if you have not already done so. | ||||
| Required Patches | Check the IP Release Notes Guide for information on any required patches. | |||