AccelDSP Synthesis Tool
MATLAB language-based design tool for implementing high performance DSP systems.
AccelDSP™ synthesis tool is a high-level MATLAB® language based tool for designing DSP blocks for Xilinx FPGAs.
- Automate floating- to fixed-point conversion
- Generate synthesizable VHDL or Verilog
- Create a testbench for verification
- Generate a fixed-point C++ model or System Generator block from a MATLAB algorithm
- A key component of the Xilinx XtremeDSP™ Tools Package and the
XtremeDSP Development Kit — Virtex®-5 Edition
Developers with little FPGA design experience can quickly create production quality FPGA implementations of DSP algorithms in a fraction of traditional RTL development times.
System Requirements
Software Requirements
- MATLAB R2007b or 2008a from The MathWorks
Tool Compatibility
Key Features
- DSP modeling – Design, architectural exploration, and debug of high-level DSP algorithms with MATLAB for Xilinx FPGAs to reduce design cycles and costs.
- IP-Explorer Technology – Heuristic-driven selection of hardware architecture at the algorithmic level to produce system-optimized designs.
- Automated floating- to fixed-point conversion – Automated word width selection and propagation for floating- to fixed-point conversion.
- Automatic code generation of synthesizable VHDL or Verilog – Bit-accurate code generated after fixed-point design meets system specifications.
- Verification of bit-accuracy – Comparison of RTL and post-place and route model for automatic verification.
- C++ simulation model generation – Improved simulations speeds of 1000x over standard fixed-point MATLAB.
- System Generator integration – Generated blocks can be exported to System Generator for inclusion in a larger system.
- Third party integration – Access to and integration of third party simulation and synthesis tools to simplify the design flow for algorithm designers unfamiliar with RTL simulation and synthesis tools.
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