Product|devboards
/csi/bk.htm
 

Xilinx : Products & Services : Development Boards : ML300 (V2PDK) General FAQs

ML300 (V2PDK) General FAQs
 
Hardware
(ml300_embedded_vhdl) I ran "make func_sim" in the ml300_embedded_vhdl design and have code in OCM but the simulation fails when it accesses the OCM.
(all designs except simple) I ran "make download" to generate PROM files but get a command-line error.
(pkt_proc - VHDL) I ran "make ba_sim" on the pkt_proc design using VHDL and get an error that "Symbol vcc has already been declared in this region"
(VHDL) I ran "make func_sim" but the BRAM INIT constants are not named properly so the simulation fails when I tried to use undefined constants.
When I am creating an ACE file for SystemACE downloading, why do I need to run "make bit" with the software set to bootloop or something similar instead of my application?
(pkt_proc, ml300_embedded_vhdl - VHDL) I ran "make func_sim" but get a ModelSim error similar to:
  "# loading...../sol/unisim.ramb16_s36_s36(ramb16_s36_s36_v)
   # ** Fatal: (vsim-3420) Array sizes do not match. Left is (2047   downto 0).
When I use a jumper to select a different JTAG Source (J204), the results I get are different from what the schematics specify on pages 3 and 26, is this an error in the schematics?
On the ml300 the ethernet PHY has a net PHY_MDINT connected to the V2P. Is this net used internally, can it be omitted?
Software
How do I know when the LED test in xrom_ml300 is finished?
xrom_ml300 software application displays strange behavior during DDR SDRAM test (program locks up or displays false memory errors).

The README docs don't seem quite right.

Other
Is some documentation missing from the CD or incorrect?
Are the microdrive contents the same as the microdrive image on CD5?
What are the Linux user/passwords?

Hardware

Q: (ml300_embedded_vhdl) I ran "make func_sim" in the ml300_embedded_vhdl design and have code in OCM but the simulation fails when it accesses the OCM.
A: The testbench does not preload ISOCM / DSOCM contents at the start of simulation. Therefore, if software is mapped to either of these, your simulation won't work correctly. You'll need to add the initialization by hand.
Q: (all designs except simple) I ran "make download" to generate PROM files but get a command-line error.
A: The flow.cfg files in these designs do not set the PROMGEN options to describe a PROM chain. Set the PROMGEN_OPT to valid PROMGEN options. Refer to the simple reference design as an example.
Q: (pkt_proc - VHDL) I ran "make ba_sim" on the pkt_proc design using VHDL and get an error that "Symbol vcc has already been declared in this region"
A: The NGD2VHDL_OPT setting in the flow.cfg file is incorrect. Remove the "-r" to not retain hierarchy.
Q: (VHDL) I ran "make func_sim" but the BRAM INIT constants are not named properly so the simulation fails when I tried to use undefined constants.
A: There is a bug in the creation of the VHDL package that defines these constants that may sometime appear if there are BRAM instances with different instance name prefixes (e.g. U1 and block_ram0). When this occurs, use sys/mem/<bmm>.vhd instead of sys/mem/<bmm>_pkg.vhd. You can do this by changing sys/vhdl/src.lst.
For instance, in the ml300_embedded_vhdl reference design, use sys/mem/memory_init.vhd instead of sys/mem/memory_init_pkg.vhd
Q: When I am creating an ACE file for SystemACE downloading, why do I need to run "make bit" with the software set to bootloop or something similar instead of my application?
A: The ACE file is composed of the FPGA bitstream + the software application. However, immediately after the FPGA bitstream portion is loaded, the PPC405 comes out of reset and begins execution. Only software that resides within the FPGA Block Select RAM (BRAM) will be initialized at this time. Therefore, if your program makes use of other memory, the program will access invalid data. Additionally, it is undesirable to begin executing now since the full application will be loaded later and start over again.

Running "make bit" generates the FPGA bitstream and by using a small program like bootloop, it can reside entirely within BRAM and idle the PPC405 until the full software application begins loading.
Q: (pkt_proc, ml300_embedded_vhdl - VHDL) I ran "make func_sim" but get a ModelSim error similar to:
  "# loading...../sol/unisim.ramb16_s36_s36(ramb16_s36_s36_v)
   # ** Fatal: (vsim-3420) Array sizes do not match. Left is (2047   downto 0).
A: There is a problem with some earlier versions of ModelSim 5.6 with the compiled VHDL unisim library and VHDL configurations. Use ModelSim 5.6b or later which do not exhibit this problem.
Q: When I use a jumper to select a different JTAG Source (J204), the results I get are different from what the schematics specify on pages 3 and 26, is this an error in the schematics?
A: Yes, the muxes drawn on page 3 and page 26 of the ML300 schematics have their "0" and "1" inputs shown reversed. The pin numbers on the schematic symbol are correct (only the graphical drawing of the mux inside the symbol is incorrect).
Q: On the ml300 the ethernet PHY has a net PHY_MDINT connected to the V2P. Is this net used internally, can it be omitted?
A: In the ML300 embedded VHDL design, a connection is missing
from the MDINT signal of the Ethenet PHY chip (FPGA I/O pin C21) to the interrupt controller core. The PHY_MDINT signal needs to be passed in from the top level, inverted, and connected to the signal "non_crit_intr(14)" in the "ip_wrapper.vhd" file. This issue does not affect the Verilog version of the design.
TOP

Software

Q: How do I know when the LED test in xrom_ml300 is finished?
A: The LED test in xrom_ml300 runs continously until you press either ESCAPE or TAB to exit the test. The message saying this unfortunately does not appear until after you press one of these keys.
Q: xrom_ml300 software application displays strange behavior during DDR SDRAM test (program locks up or displays false memory errors).
A:

The mapfile for the ml300 application has the stack and heap set to be too large so this may cause the program to access stack/heap space that overruns into the memory region under test.
To solve this problem, edit $V2PRO/source/sw_old/mapfiles/mapfile_ml300 and change to the following:

 

STACKSIZE

=

128k;

 

HEAPSIZE

=

512k;

After these changes are made, recompile the xrom_ml300 application:
   cd $V2PRO/source/sw_old/apps/xrom_ml300
   make clean all
Q: The README docs don't seem quite right.
A:

README files are incorrect or missing for $V2PRO/source/sw_old:
   bootload
   hello_tft
   dispbmp
   ledfade
   pkt_proc
   scalechar
   touchcalibrate
   v2pdraw
   v2ptictac

TOP
Other
Q: Is some documentation missing from the CD or incorrect?
A: Yes. The CD contains preliminary documentation from an earlier version that may be inaccurate in some areas that have recently changed. The latest documentation should be used - it can be found at http://www.xilinx.com/products/boards/ml300/docs.htm.

If you do read the documentation on the CD, please note the following:
- The preliminary documentation that comes with the CD refers to "source/sw". In V2PDK 1.5, this is now "source/sw_old" Additionally, this documentation is out-of-date and therefore inaccurate in certain areas
- The V2PDK 1.5 "source/sw" is self-documented within the code; there is no further documentation for it on the CD
- There is no included documentation for GDB
Q: Are the microdrive contents the same as the microdrive image on CD5?
A: No. The CD has a timed out bitstream with a very stripped down version of Linux. The Microdrive has the full version of Linux with Xwindows without the bitstream time out.
Q: What are the Linux user/passwords ?
A:

The passwords for the Microdrive version of Linux:

  User: linux
  Password: ml300
  User: root
  Password: 300ml
The passwords for the CD5 version of Linux (blank password):
  User: root
  Password:
 
ML300 (V2PDK) Install FAQs
ML300 (V2PDK) Getting Started (PDF)
ML300 (V2PDK) User Guide (PDF)
ML300 (V2PDK) Overview
ML300 (V2PDK) Resources
ML300 (V2PDK) Lounge
   
/csi/footer.htm